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UJA1079ATW/3V3/WDJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 16 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
6.3 On-chip oscillator
The on-chip oscillator provides the timing reference for the on-chip watchdog and the
internal timers. The on-chip oscillator is supplied by an internal supply that is connected to
V
BAT
and is independent of V1.
6.4 Watchdog (UJA1079A/xx/WD versions)
Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is
programmed via the NWP control bits in the WD_and_Status register (see Table 4
). The
default watchdog period is 128 ms.
A watchdog trigger event is any write access to the WD_and_Status register. When the
watchdog is triggered, the watchdog timer is reset.
In watchdog Window mode, a watchdog trigger event within a closed watchdog window
(i.e. the first half of the window before t
trig(wd)1
) will generate an SBC reset. If the watchdog
is triggered before the watchdog timer overflows in Timeout or Window mode, or within
the open watchdog window (after t
trig(wd)1
but before t
trig(wd)2
), the timer restarts
immediately.
The following watchdog events result in an immediate system reset:
• the watchdog overflows in Window mode
• the watchdog is triggered in the first half of the watchdog period in Window mode
• the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending
• the state of the WDOFF pin changes in Normal mode or Standby mode
• the watchdog mode control bit (WMC) changes state in Normal mode
After a watchdog reset (short reset; see Section 6.5.1
and Table 11), the default watchdog
period is selected (NWP = 100). The watchdog can be switched off completely by forcing
pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in
Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will
re-enable it.
Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is
pending. Any attempt to change WMC when an interrupt is pending will be ignored.
6.4.1 Watchdog Window behavior
The watchdog runs continuously in Window mode.
If the watchdog overflows, or is triggered in the first half of the watchdog period (less than
t
trig(wd)1
after the start of the watchdog period), a system reset will be performed.
Watchdog overflow occurs if the watchdog is not triggered within t
trig(wd)2
after the start of
the watchdog period.
If the watchdog is triggered in the second half of the watchdog period (at least t
trig(wd)1
, but
not more than t
trig(wd)2
, after the start of the watchdog period), the watchdog will be reset.
The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode
and the watchdog mode control bit (WMC) is set to 0.
UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 17 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
6.4.2 Watchdog Timeout behavior
The watchdog runs continuously in Timeout mode. It can be reset at any time by a
watchdog trigger. If the watchdog overflows, the CI bit is set. If a CI is already pending, a
system reset is performed.
The watchdog is in Timeout mode when pin WDOFF is LOW and:
• the SBC is in Standby mode and bit WMC = 0 or
• the SBC is in Normal mode and bit WMC = 1
6.4.3 Watchdog Off behavior
The watchdog is disabled in this state.
The watchdog is in Off mode when:
• the SBC is in Off, Overtemp or Sleep modes
• the SBC is in Standby mode and bit WMC = 1
• the SBC is in any mode and the WDOFF pin is HIGH
6.5 System reset
The following events will cause the SBC to perform a system reset:
• V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN
pin)
• An external reset (pin RSTN forced LOW)
• Watchdog overflow (Window mode)
• Watchdog overflow in Timeout mode with CI pending
• Watchdog triggered too early in Window mode
• WMC value changed in Normal mode
• WDOFF pin state changed
• SBC goes to Sleep mode (MC set to 01; see Table 5) while pin INTN is driven LOW
• SBC goes to Sleep mode (MC set to 01; see Table 5) while
STBCL = WIC1 = WIC2 = 0
• SBC goes to Sleep mode (MC set to 01; see Table 5) while wake-up pending
• Software reset (SWR = 1)
• SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor
on RSTN pin)
A watchdog overflow in Timeout mode requests a CI, if a CI is not already pending.
The UJA1079A provides three signals for dealing with reset events:
• RSTN pin input/output for performing a global ECU system reset or forcing an
external reset
• EN pin, a fail-safe global enable output
• LIMP pin, a fail-safe limp home output
UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 18 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
6.5.1 RSTN pin
A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t
fltr
by
the microcontroller (external reset). A reset pulse is output on pin RSTN by the SBC when
a system reset is triggered internally.
The reset pulse width (t
w(rst)
) is selectable (short or long) if the system reset was
generated by a V1 undervoltage event (see Section 6.6.2
) or by the SBC leaving Off
(V
BAT
> V
th(det)pon
) or Overtemp (temperature < T
th(rel)otp
) modes. A short reset pulse is
selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1. If a resistor is
not connected, the reset pulse will be long (see Table 11
).
In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.
6.5.2 EN output
The EN pin can be used to control external hardware, such as power components, or as a
general-purpose output when the system is running properly.
In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in
the Mode_Control register; see Table 5
) via the SPI interface. Pin EN will be HIGH when
ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior
is illustrated in Figure 5
.
6.5.3 LIMP output
The LIMP pin can be used to enable the so called ‘limp home’ hardware in the event of an
ECU failure. Detectable failure conditions include SBC overtemperature events, loss of
watchdog service, pins RSTN or V1 clamped LOW and user-initiated or external reset
events.
The LIMP pin is a battery-related, active-LOW, open-drain output.
A system reset will cause the limp home warning control bit (bit LHWC in the
Mode_Control register; see Table 5
) to be set. If LHWC is already set when the system
reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application
should clear LHWC after each reset event to ensure the LIMP output is not activated
during normal operation.
In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always
active. If the application manages to recover from the event that activated the LIMP
output, LHC can be cleared to deactivate the LIMP output.
Fig 5. Behavior of EN pin
RSTN
EN
ENC
mode
STANDBY NORMAL STANDBY
015aaa07
4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

UJA1079ATW/3V3/WDJ

Mfr. #:
Buy UJA1079ATW/3V3/WDJ
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1079ATW/HTSSOP32//3V3/WD/1/REEL 13 Q1 NDP
Lifecycle:
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