UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 23 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
6.7.2 Fail-safe features
6.7.2.1 General fail-safe features
The following fail-safe features have been implemented:
• Pin TXDL has an internal pull-up towards V
V1
to guarantee safe, defined states if
these pins are left floating
• The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
• A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus.
6.7.2.2 TXDL dominant time-out function
A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent
dominant state (blocking all network communications) if pin TXDL is forced permanently
LOW by a hardware and/or software application failure. The timer is triggered by a
negative edge on the TXDL pin. If the pin remains LOW for longer than the TXDL
dominant time-out time (t
to(dom)TXDL
), the transmitter is disabled, driving the bus lines to a
recessive state. The timer is reset by a positive edge on the TXDL pin.
6.8 Local wake-up input
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register Table 6
). These bits can also be used to disable
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4
).
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
Fig 11. Wake-up pin sampling synchronized with WBIAS signal
Wake-up int
WAKEx pin
WBIAS pin
WBIASI
(internal)
enable bias disable bias
disable bias
wake level latched
015aaa07
