LTC4266CIUHF#TRPBF Datasheet LTC4266AIUHF-4#PBF, LTC4266CIUHF#PBF, LTC4266AIUHF-2#PBF | P13-P15

LTC4266A/LTC4266C

4266acfd

For more information www.linear.com/LTC4266A

PIN FUNCTIONS

RESET: Chip Reset, Active Low. When the RESET pin is

low, the LTC4266A/LTC4266C is held inactive with all ports

off and all internal registers reset to their power-up states.

When RESET is pulled high, the LTC4266A/LTC4266C

begins normal operation. RESET can be connected to

an external capacitor or RC network to provide a power

turn-on delay. Internal filtering of the RESET pin prevents

glitches less than 1µs wide from resetting the LTC4266A/

LTC4266C. Internally pulled up to V

MID: Midspan Mode Input. When high, the LTC4266A/

LTC4266C acts as a midspan device. Internally pulled

down to DGND.

INT: Interrupt Output, Open Drain. INT will pull low when any

one of several events occur in the LTC4266A/LTC4266C.

It will return to a high impedance state when bits 6 or 7

are set in the Reset PB register (1Ah). The INT signal can

be used to generate an interrupt to the host processor,

eliminating the need for continuous software polling.

Individual INT events can be disabled using the Int Mask

Programming documentation for more information.

The

INT pin is only updated between I

C transactions.

SCL: Serial Clock Input. High impedance clock input for the

C serial interface bus. SCL must be tied high if not used.

SDAOUT: Serial Data Output, Open Drain Data Output for

the I

C Serial Interface Bus. The LTC4266A/LTC4266C

uses two pins to implement the bidirectional SDA function

to simplify optoisolation of the I

C bus. To implement a

standard bidirectional SDA pin, tie SDAOUT and SDAIN

together. SDAOUT should be grounded or left floating if

not used. See the Applications Information section for

more information.

SDAIN: Serial Data Input. High impedance data input for

the I

C serial interface bus. The LTC4266A/LTC4266C

uses two pins to implement the bidirectional SDA function

to simplify optoisolation of the I

C bus. To implement a

standard bidirectional SDA pin, tie SDAOUT and SDAIN

together. SDAIN must be tied high if not used. See the

Applications Information section for more information.

AD3: Address Bit 3. Tie the address pins high or low to set

the I

C serial address to which the LTC4266A/LTC4266C

responds. This address will be 010A

b. Internally

pulled up to V

AD2: Address Bit 2. See AD3.

AD1: Address Bit 1. See AD3.

AD0: Address Bit 0. See AD

NC, DNC: All pins identified with “NC” or “DNC” must be

left unconnected.

DGND: Digital Ground. DGND is the return for the V

supply.

: Logic Power Supply. Connect to a 3.3V power supply

relative to DGND. V

must be bypassed to DGND near

the LTC4266A/LTC4266C with at least a 0.1µF capacitor.

SHDN1: Shutdown Port 1, Active Low. When pulled low,

SHDN1 shuts down port 1, regardless of the state of the

internal registers. Pulling SHDN1 low is equivalent to set-

ting the Reset Port 1 bit in the Reset Pushbutton register

(1Ah). Internal filtering of the SHDN1 pin prevents glitches

less than 1µs wide from resetting the port. Internally

pulled up to V

SHDN2: Shutdown Port 2, Active Low. See SHDN1.

SHDN3: Shutdown Port 3, Active Low. See SHDN1.

SHDN4: Shutdown Port 4, Active Low. See SHDN1.

AGND: Analog Ground. AGND is the return for the V

supply.

SENSE4:

Port 4 Current Sense Input. SENSE4 monitors

the external MOSFET current via a 0.5Ω or 0.25Ω sense

resistor between SENSE4 and V

. Whenever the voltage

across the sense resistor exceeds the overcurrent detection

threshold V

CUT

, the current limit fault timer counts up. If

the voltage across the sense resistor reaches the current

limit threshold V

LIM

, the GATE4 pin voltage is lowered to

maintain constant current in the external MOSFET. See

the Applications Information section for further details.

If the port is unused, the SENSE4 pin must be tied to V

LTC4266A/LTC4266C

4266acfd

For more information www.linear.com/LTC4266A

PIN FUNCTIONS

GATE4: Port 4 Gate Drive. GATE4 should be connected

to the gate of the external MOSFET for port 4. When the

MOSFET is turned on, the gate voltage is driven to 12V

(typ) above V

. During a current limit condition, the

voltage at GATE4 will be reduced to maintain constant

current through the external MOSFET. If the fault timer

expires, GATE4 is pulled down, turning the MOSFET off

and recording a t

CUT

or t

START

event. If the port is unused,

float the GATE4 pin.

OUT4: Port 4 Output Voltage Monitor. OUT4 should be

connected to the output port. A current limit foldback

circuit limits the power dissipation in the external MOSFET

by reducing the current limit threshold when the drain-to-

source voltage exceeds 10V. The port 4 Power Good bit is

set when the voltage from OUT4 to V

drops below 2.4V

(typ). A 500k resistor is connected internally from OUT4

to AGND when the port is idle. If the port is unused, OUT4

pin must be floated.

SENSE3: Port 3 Current Sense Input. See SENSE4.

GATE3: Port 3 Gate Drive. See GATE4.

OUT3: Port 3 Output Voltage Monitor. See OUT4.

: Main Supply Input. Connect to a –45V to –57V

supply, relative to AGND.

SENSE2: Port 2 Current Sense Input. See SENSE4.

GATE2: Port 2 Gate Drive. See GATE4.

OUT2: Port 2 Output Voltage Monitor. See OUT4.

SENSE1: Port 1 Current Sense Input. See SENSE4.

GATE1: Port 1 Gate Drive. See GATE 4.

OUT1: Port 1 Output Voltage Monitor. See OUT4.

AUTO: AUTO Pin Mode Input. AUTO pin mode allows the

LTC4266A/LTC4266C to detect and power up a PD even

if there is no host controller present on the I

C bus. The

voltage of the AUTO pin determines the state of the internal

registers when the LTC4266A/LTC4266C is reset or comes

out of V

UVLO (see the LTC4266A/LTC4266C Software

Programming documentation). The states of these register

bits can subsequently be changed via the I

C interface.

The real-time state of the AUTO pin is read at bit 0 in the

Pin Status register (11h). Internally pulled down to DGND.

Must be tied locally to either V

or DGND.

MSD: Maskable Shutdown Input. Active low. When pulled

low, all ports that have their corresponding mask bit set

in the Misc Config register (17h) will be reset, equivalent

to pulling the SHDN pin low.

Internal filtering of the MSD

pin prevents glitches less than 1µs wide from resetting

ports. Internally pulled up to V

LTC4266A/LTC4266C

4266acfd

For more information www.linear.com/LTC4266A

Overview

Power over Ethernet, or PoE, is a standard protocol for

sending DC power over copper Ethernet data wiring.

The IEEE group that administers the 802.3 Ethernet data

standards added PoE powering capability in 2003. This

original PoE spec, known as 802.3af, allowed for 48V DC

power at up to 13W. This initial spec was widely popular,

but 13W was not adequate for some requirements. In

2009, the IEEE released a new standard, known as 802.3at

or PoE

, increasing the voltage and current requirements

to provide 25W of power.

The IEEE standard also defines PoE terminology. A device

that provides power to the network is known as a PSE, or

power sourcing equipment, while a device that draws power

from the network is known as a PD, or powered device.

PSEs come in two types: Endpoints (typically network

switches or routers), which provide data and power; and

Midspans, which provide power but pass through data.

Midspans are typically used to add PoE capability to existing

non-PoE networks. PDs are typically IP phones, wireless

access points, security cameras, and similar devices.

PoE

Evolution

Even during the process of creating the IEEE PoE

25.5W

specification, it became clear that there was a significant

and increasing need for more than 25.5W of delivered

power. The LTC4266A family responds to this market by

allowing a reliable means of providing up to 90W of deliv-

ered power to a LTPoE

PD. The LTPoE

specification

provides reliable detection and classification extensions to

the existing IEEE PoE technique that are backward com-

patible and interoperable with existing Type 1 and Type 2

PDs.

Unlike other proprietary PoE

solutions, Linear’s

LTPoE

solution provides mutual identification between

the PSE and PD. This ensures that the LTPoE

PD knows

it may use the requested power at start-up because it has

detected a LTPoE

PSE. LTPoE

PSEs can differentiate

between a LTPoE

PD and all other types of IEEE compli-

ant PDs allowing LTPoE

PSEs to remain compliant and

interoperable with existing equipment.

LTC4266 Product Family

The LTC4266 is a third-generation quad PSE controller

that implements four PSE ports in either an end-point or

midspan design. Virtually all necessary circuitry is included

to implement an IEEE 802.3at compliant PSE design,

requiring only an external power MOSFET and sense resis-

tor per channel; these minimize power loss compared to

alternative designs with on-board MOSFETs and increase

system reliability in the event a single channel fails.

The LTC4266 comes in three grades which support dif-

ferent PD power levels.

The A-grade LTC4266 extends PoE power delivery capa-

bilities to LTPoE

levels. LTPoE

is a Linear Technology

proprietary specification allowing for the delivery of up to

90W to LTPoE

compliant PDs. The LTPoE

architecture

extends the IEEE physical power negotiation to include

38.7W, 52.7W, 70W and 90W power levels. The A-grade

LTC4266 also incorporates all B- and C-grade features.

The B-grade LTC4266 is a fully IEEE-compliant Type 2

PSE supporting autonomous detection, classification

and powering of Type 1 and Type 2 PDs. The B-grade

LTC4266 also incorporates all C-grade features. The

B-grade LTC4266 is marketed and numbered without the

B suffix for legacy reasons; the absence of power grade

suffix infers a B-grade part

The C-grade LTC4266 is a fully autonomous 802.3at Type 1

PSE solution. Intended for use only in AUTO pin mode,

the C-grade chipset autonomously supports detection,

classification and powering of Type 1 PDs. As a Type 1

PSE, 2-event classification is prohibited and Class 4 PDs

are automatically treated as Class 0 PDs.

PoE Basics

Common Ethernet data connections consist of two or four

twisted pairs of copper wire (commonly known as CAT-5

cable), transformer-coupled at each end to avoid ground

loops. PoE systems take advantage of this coupling ar-

rangement by applying voltage between the center-taps

of the data transformers to transmit power from the PSE

to the PD without affecting data transmission. Figure 10

shows a high-level PoE system schematic.

OPERATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

LTC4266CIUHF#TRPBF

Mfr. #:

Buy LTC4266CIUHF#TRPBF

Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN PoE 13W Quad PSE Controller

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LTC4266CIUHF#TRPBF

LTC4266CIUHF#TRPBF

Products related to this Datasheet