LTC4266CIUHF#TRPBF Datasheet LTC4266AIUHF-4#PBF, LTC4266CIUHF#PBF, LTC4266AIUHF-2#PBF | P22-P24

LTC4266A/LTC4266C

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APPLICATIONS INFORMATION

Per the IEEE specification, the LTC4266A/LTC4266C will

allow the port current to exceed I

CUT

for a limited period of

time before removing power from the port, whereas it will

actively control the MOSFET gate drive to keep the port cur-

rent below I

LIM

. The port does not take any action to limit the

current when only the I

CUT

threshold is exceeded, but does

start the t

CUT

timer. If the current drops below the I

CUT

cur-

rent threshold before its timer expires, the t

CUT

timer counts

back down, but at 1/16 the rate that it counts up. If the t

CUT

timer reaches 60ms (typical) the port is turned off and the

port t

CUT

fault is set. This allows the current limit circuitry to

tolerate intermittent overload signals with duty cycles below

about 6%; longer duty cycle overloads will turn the port off.

The I

LIM

current limiting circuit is always enabled and

actively limiting port current. The t

LIM

timer is enabled

only when the programmable t

LIMn

field is non-zero. This

allows t

LIM

to be set to a shorter value than t

CUT

to provide

more aggressive MOSFET protection and turn off a port

before MOSFET damage can occur. The t

LIM

timer starts

when the I

LIM

threshold is exceeded. When the t

LIM

timer

reaches 1.7ms (typ) times the programmable t

LIMn

field the

port is turned off and the port t

LIM

fault is set. When the

LIMn

field is zero, t

LIM

behaviors are tracked by the t

CUT

timer, which counts up during both I

LIM

and I

CUT

events.

CUT

is typically set to a lower value than I

LIM

to allow the

port to tolerate minor faults without current limiting.

Per the IEEE specification, the LTC4266A/LTC4266C will

automatically set I

LIM

to 425mA (shown in bold in Table 6)

during inrush at port turn-on, and then switch to the

programmed I

LIM

setting once inrush has completed.

To maintain IEEE compliance, I

LIM

should be kept at 425mA

for all Type 1 PDs, and 850mA if a Type 2 PD is detected.

LIM

is automatically reset to 425mA when a port turns off.

LIM

Foldback

The LTC4266A/LTC4266C features a two-stage foldback

circuit that reduces the port current if the port voltage falls

below the normal operating voltage. This keeps MOSFET

power dissipation at safe levels for typical 802.3af MOS-

FETs, even at extended 802.3at power levels. Current

limit and foldback behavior are programmable on a per-

port basis. Table 6 gives examples of recommended I

LIM

Table 6. Example Current Limit Settings

LIM

(mA)

INTERNAL REGISTER SETTING (hex)

SENSE

= 0.5Ω R

SENSE

= 0.25Ω

53 88

106 08 88

159 89

213 80 08

266 8A

319 09 89

372 8B

425 00 80

478 8E

531 92 8A

584 CB

638 10 90

744 D2 9A

850 40 C0

956 4A CA

1063 50 D0

1169 5A DA

1275 60 E0

1488 52 49

1700 40

1913 4A

2125 50

2338 5A

2550 60

2975 52

The LTC4266A/LTC4266C will support current levels well

beyond the maximum values in the 802.3at specification. The

shaded areas in Table 6 indicate settings that may require a

larger external MOSFET, additional heat sinking, or enabling t

LIM

MOSFET Fault Detection

LTC4266A/LTC4266C PSE ports are designed to tolerate

significant levels of abuse

, but in extreme cases it is pos-

sible for the external MOSFET to be damaged. A failed

MOSFET may short source to drain, which will make the

port appear to be on when it should be off; this condition

may also cause the sense resistor to fuse open, turning

off the port but causing the LTC4266A/LTC4266C SENSE

pin to rise to an abnormally high voltage. A failed MOSFET

LTC4266A/LTC4266C

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APPLICATIONS INFORMATION

may also short from gate to drain, causing the LTC4266A/

LTC4266C GATE pin to rise to an abnormally high voltage.

The LTC4266A/LTC4266C OUT, SENSE and GATE pins

are designed to tolerate up to 80V faults without damage.

If the LTC4266A/LTC4266C sees any of these conditions

for more than 180μs, it disables all port functionality,

reduces the gate drive pull-down current for the port and

reports a FET Bad fault. This is typically a permanent fault,

but the host can attempt to recover by resetting the port,

or by resetting the entire chip if a port reset fails to clear

the fault. If the MOSFET is in fact bad, the fault will quickly

return, and the port will disable itself again. The remaining

ports of the LTC4266A/LTC4266C are unaffected.

An open or missing MOSFET will not trigger a FET Bad fault,

but will cause a t

START

fault if the LTC4266A/LTC4266C

attempts to turn on the port.

Voltage and Current Readback

The LTC4266A/LTC4266C measures the output voltage

and current at each port with an internal A/D converter.

Port data is only valid when the port power is on. The

converter has two modes:

• Slow mode: 14 samples per second, 14.5 bits resolution

• Fast mode: 440 samples per second, 9.5 bits resolution

In fast mode, the least significant 5 bits of the lower byte

are zeroes so that bit scaling is the same in both modes.

Disconnect

The LTC4266A/LTC4266C monitors the port to make

sure that the PD continues to draw the minimum speci-

fied current. A disconnect timer counts up whenever port

current is below 7.5mA (typ), indicating that the PD has

been disconnected. If the t

DIS

timer expires, the port will

be turned off and the disconnect bit in the fault event reg-

ister will be set. If the current returns before the t

DIS

timer

runs out, the timer resets and will start counting from the

beginning if the undercurrent condition returns. As long

as the PD exceeds the minimum current level more often

than t

DIS

, it will stay powered.

Although not recommended, the DC disconnect feature can

be disabled by clearing the corresponding DC Disconnect

Enable bits. Note that this defeats the protection mecha-

nisms built into the IEEE spec, since a powered port will

stay powered after the PD is removed. If the still-powered

port is subsequently connected to a non-PoE data device,

the device may be damaged.

The LTC4266A/LTC4266C does not include AC disconnect

circuitry, but includes AC Disconnect Enable bits to main-

tain compatibility with the LTC4259A. If the AC Disconnect

Enable bits are set, DC disconnect will be used.

Shutdown Pins

The LTC4266A/LTC4266C includes a hardware SHDN pin

for each port. When a SHDN pin is pulled to DGND, the

corresponding port will be shut off immediately. The port

remains shut down until re-enabled via I

C or a device

reset in AUTO pin mode.

Masked Shutdown

The LTC4266

A/LTC4266C provides a low latency port

shedding feature to quickly reduce the system load when

required. By allowing a pre-determined set of ports to

be turned off, the current on an overloaded main power

supply can be reduced rapidly while keeping high priority

devices powered. Each port can be configured to high or

low priority; all low-priority ports will shut down within

6.5μs after the MSD pin is pulled low. If multiple ports in

a LTC4266A/LTC4266C device are shut down via MSD,

they are staggered by at least 0.55μs to help reduce volt-

age transients on the main supply. If a port is turned off

via MSD, the corresponding Detection and Classification

Enable bits are cleared, so the port will remain off until

the host explicitly re-enables detection.

SERIAL DIGITAL INTERFACE

Overview

The LTC4266A/LTC4266C communicates with the host us-

ing a standard SMBus/I

C 2-wire interface. The LTC4266A/

LTC4266C is a slave-only device, and communicates with

the host master using the standard SMBus protocols.

Interrupts are signaled to the host via the INT pin. The

Timing Diagrams (Figures 5 through 9) show typical

LTC4266A/LTC4266C

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communication waveforms and their timing relationships.

More information about the SMBus data protocols can be

found at www.smbus.org.

The LTC4266A/LTC4266C requires both the V

and V

supply rails to be present for the serial interface to function.

Bus Addressing

The LTC4266A/LTC4266C’s primary serial bus address

is 010xxxxb, with the lower four bits set by the AD3-AD0

pins; this allows up to 16 LTC4266A/LTC4266Cs on a

single bus. All LTC4266A/LTC4266Cs also respond to

the address 0110000b, allowing the host to write the

same command (typically configuration commands) to

multiple LTC4266A/LTC4266Cs in a single transaction. If

the LTC4266A/LTC4266C is asserting the INT pin, it will

also respond to the alert response address (0001100b)

per the SMBus spec.

Interrupts and SMBAlert

Most LTC4266A/LTC4266C port events can be configured

to trigger an interrupt, asserting the INT pin and alerting

the host to the event. This removes the need for the host

to poll the LTC4266A/LTC4266C, minimizing serial bus

traffic and conserving host CPU cycles. Multiple LTC4266A/

LTC4266Cs can share a common INT line, with the host

using the SMBAlert protocol (ARA) to determine which

LTC4266A/LTC4266C caused an interrupt.

For information on serial bus usage and device configura-

tion and status, refer to the LTC4266A/LTC4266C Software

Programming documentation.

EXTERNAL COMPONENT SELECTION

Power Supplies and Bypassing

The LTC4266A/LTC4266C requires two supply voltages to

operate. V

requires 3.3V (nominally) relative to DGND.

requires a negative voltage of between –45V and –57V

for Type

1 PSEs, –51V to –57V for Type 2 PSEs or –54.75V

to –57V for LTPoE

PSEs, relative to AGND. The relation-

ship between the two grounds is not fixed; AGND can be

referenced to any level from V

to DGND, although it

should typically be tied to either V

or DGND.

provides power for most of the internal LTC4266A/

LTC4266C circuitry, and draws a maximum of 3mA. A

ceramic decoupling cap of at least 0.1μF should be placed

from V

to DGND, as close as practical to each LTC4266A/

LTC4266C chip.

Figure 14 shows a three component low dropout regula-

tor for a negative supply to DGND generated from the

negative V

supply. V

is tied to AGND and DGND is

negative referenced to AGND. This regulator drives a single

LTC4266A/LTC4266C device. In Figure 15, DGND is tied

to AGND in this boost converter circuit for a positive V

supply of 3.3V above AGND. This circuit can drive multiple

LTC4266A/LTC4266C devices and opto couplers.

is the main supply that provides power to the PDs.

Because it supplies a relatively large amount of power and

is subject to significant current transients, it requires more

design care than a simple logic supply. For minimum IR

loss and best system efficiency, set V

near maximum

amplitude (57V), leaving enough margin to account for

transient over- or undershoot, temperature drift, and the

line regulation specs of the particular power supply used.

Bypass capacitance between AGND and V

is very im-

portant for reliable operation. If a short-circuit occurs at

one of the output ports it can take as long as 1μs for the

LTC4266A/LTC4266C to begin regulating the current.

During this time the current is limited only by the small

impedances in the circuit and a high current spike typically

occurs, causing a voltage transient on the V

supply and

possibly causing the LTC4266A/LTC4266C to reset due

to a UVLO fault. A 1μF, 100V X7R capacitor placed near

the V

pin is recommended to minimize spurious resets.

APPLICATIONS INFORMATION

Figure 14. Negative LDO to DGND

4266AC F14

750k

CMHZ4687-4.3V

0.1µF

CMPTA92

LTC4266

AGND

DGND

10Ω

SMAJ58A

1µF

100V

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LTC4266CIUHF#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN PoE 13W Quad PSE Controller

Lifecycle:

New from this manufacturer.

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