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7205L12P

P1-P3P4-P6P7-P9P10-P12P13-P14
4
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Commercial Com'l & Ind'l Com'l & Military Commercial Com'l & Ind'l
IDT7203L12 IDT7203L15
(2)
IDT7203L20 IDT7208L20 IDT7203L25
(2)
IDT7204L12 IDT7204L15
(2)
IDT7204L20 IDT7204L25
(2)
IDT7205L12 IDT7205L15
(2)
IDT7205L20 IDT7205L25
(2)
IDT7206L15 IDT7206L20 IDT7206L25
(3)
IDT7207L15 IDT7207L20 IDT7207L25
(3)
IDT7208L25
(3)
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency — 50 — 40 — 33.3 — 33.3 — 28.5 MH z
tRC Read Cycle Time 20 — 25 — 30 — 30 — 35 — ns
tA Access Time — 12 — 15 — 20 — 20 — 25 ns
tRR Read Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tRPW Read Pulse Width
(4)
12 — 15 — 20 — 20 — 25 — ns
tRLZ Read LOW to Data Bus LOW
(5)
3—5 —5—5—5—ns
tWLZ Write HIGH to Data Bus Low-Z
(5,6)
3—5 —5—5—5—ns
tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — 5 — ns
tRHZ Read HIGH to Data Bus High-Z
(5)
—12— 15—15—15—18ns
tWC Write Cycle Time 20 — 25 — 30 — 30 — 35 — ns
tWPW Write Pulse Width
(4)
12 — 15 — 20 — 20 — 25 — ns
tWR Write Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tDS Data Set-up Time 9 — 11 — 12 — 12 — 15 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns
tRSC Reset Cycle Time 20 — 25 — 30 — 30 — 35 — ns
tRS Reset Pulse Width
(4)
12 — 15 — 20 — 20 — 25 — ns
tRSS Reset Set-up Time
(5)
12 — 15 — 20 — 20 — 25 — ns
tRTR Reset Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tRTC Retransmit Cycle Time 20 — 25 — 30 — 30 — 35 — ns
tRT Retransmit Pulse Width
(4)
12 — 15 — 20 — 20 — 25 — ns
tRTS Retransmit Set-up Time
(5)
12 — 15 — 20 — 20 — 25 — ns
tRTR Retransmit Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tEFL Reset to EF LOW —12— 25—30—30—35ns
tHFH, tFFH Reset to HF and FF HIGH — 17 — 25 — 30 — 30 — 35 ns
tRTF Retransmit LOW to Flags Valid — 20 — 25 — 30 — 30 — 35 ns
tREF Read LOW to EF LOW —12— 15—20—20—25ns
tRFF Read HIGH to FF HIGH — 14 — 15 — 20 — 20 — 25 ns
tRPE Read Pulse Width after EF HIGH 12 — 15 — 20 — 20 — 25 — ns
tWEF Write HIGH to EF HIGH — 12 — 15 — 20 — 20 — 25 ns
tWFF Write LOW to FF LOW —14— 15—20—20—25ns
tWHF Write LOW to HF Flag LOW — 17 — 25 — 30 — 30 — 35 ns
tRHF Read HIGH to HF Flag HIGH — 17 — 25 — 30 — 30 — 35 ns
tWPF Write Pulse Width after FF HIGH 12 — 15 — 20 — 20 — 25 — ns
tXOL Read/Write LOW to XO LOW —12— 15—20—20—25ns
tXOH Read/Write HIGH to XO HIGH — 12 — 15 — 20 — 20 — 25 ns
tXI XI Pulse Width
(4)
12 — 15 — 20 — 20 — 25 — ns
tXIR XI Recovery Time 8 — 10 — 10 — 10 — 10 — ns
t
XIS XI Set-up Time 8 — 10 — 10 — 10 — 10 — ns
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.
3. Industrial temperature range product for 25ns speed grade only is available as a standard device. All other speed grades are available by special order.
4. Pulse widths less than minimum are not allowed.
5. Values guaranteed by design, not currently tested.
6. Only applies to read data flow-through mode.
5
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
AC ELECTRICAL CHARACTERISTICS
(1)
(CONTINUED)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
Military Commercial Military Commercial
IDT7203L30 IDT7203L35 IDT7203L40 IDT7203L50
IDT7204L30 IDT7204L35 IDT7204L50
IDT7205L30 IDT7205L35 IDT7205L50
IDT7206L30 IDT7206L35 IDT7206L50
IDT7207L30 IDT7207L35 IDT7207L50
IDT7208L35
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency — 25 — 22.22 — 20 — 15 M Hz
tRC Read Cycle Time 40 — 45 — 50 — 65 — ns
tA Access Time — 30 — 35 — 40 — 50 ns
tRR Read Recovery Time 10 — 10 — 10 — 15 — ns
tRPW Read Pulse Width
(2)
30 — 35 — 40 — 50 — ns
tRLZ Read LOW to Data Bus LOW
(3)
5— 5—5—10—ns
tWLZ Write HIGH to Data Bus Low-Z
(3,4)
5 — 10 — 10 — 15 — ns
tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — ns
tRHZ Read HIGH to Data Bus High-Z
(3)
—20 —20—25—30ns
tWC Write Cycle Time 40 — 45 — 50 — 65 — ns
tWPW Write Pulse Width
(2)
30 — 35 — 40 — 50 — ns
tWR Write Recovery Time 10 — 10 — 10 — 15 — ns
tDS Data Set-up Time 18 — 18 — 20 — 30 — ns
tDH Data Hold Time 0 — 0 — 0 — 5 — ns
tRSC Reset Cycle Time 40 — 45 — 50 — 65 — ns
tRS Reset Pulse Width
(2)
30 — 35 — 40 — 50 — ns
tRSS Reset Set-up Time
(3)
30 — 35 — 40 — 50 — ns
tRTR Reset Recovery Time 10 — 10 — 10 — 15 — ns
tRTC Retransmit Cycle Time 40 — 45 — 50 — 65 — ns
tRT Retransmit Pulse Width
(2)
30 — 35 — 40 — 50 — ns
tRTS Retransmit Set-up Time
(3)
30 — 35 — 40 — 50 — ns
tRTR Retransmit Recovery Time 10 — 10 — 10 — 15 — ns
tEFL Reset to EF LOW —40 —45—50—65ns
tHFH, tFFH Reset to HF and FF HIGH — 40 — 45 — 50 — 65 ns
tRTF Retransmit LOW to Flags Valid — 40 — 45 — 50 — 65 ns
tREF Read LOW to EF LOW —30 —30—35—45ns
tRFF Read HIGH to FF HIGH — 30 — 30 — 35 — 45 ns
tRPE Read Pulse Width after EF HIGH 30 — 35 — 40 — 50 — ns
tWEF Write HIGH to EF HIGH — 30 — 30 — 35 — 45 ns
tWFF Write LOW to FF LOW —30 —30—35—45ns
tWHF Write LOW to HF Flag LOW — 40 — 45 — 50 — 65 ns
tRHF Read HIGH to HF Flag HIGH — 40 — 45 — 50 — 65 ns
tWPF Write Pulse Width after FF HIGH 30 — 35 — 40 — 50 — ns
tXOL Read/Write LOW to XO LOW —30 —35—40—50ns
tXOH Read/Write HIGH to XO HIGH — 30 — 35 — 40 — 50 ns
tXI XI Pulse Width
(2)
30 — 35 — 40 — 50 — ns
tXIR XI Recovery Time 10 — 10 — 10 — 10 — ns
tXIS XI Set-up Time 10 — 15 — 15 — 15 — ns
6
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
loaded (see Operating Modes). The Single Device Mode is initiated by grounding
the Expansion In (XI).
The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data
when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit
operation will set the internal read pointer to the first location and will not affect the
write pointer. The status of the Flags will change depending on the relative locations
of the read and write pointers. Read Enable (R) and Write Enable (W) must be
in the HIGH state during retransmit. This feature is useful when less than 2,048/
4,096/8,192/16,384/32,768/65,536 writes are performed between resets. The
retransmit feature is not compatible with the Depth Expansion Mode.
EXPANSION IN ( XI ) — This input is a dual-purpose pin. Expansion In (XI)
is grounded to indicate an operation in the single device mode. Expansion In (XI)
is connected to Expansion Out (XO) of the previous device in the Depth Expansion
or Daisy-Chain Mode.
OUTPUTS:
FULL FLAG ( FF ) — The Full Flag (FF) will go LOW, inhibiting further write
operations, when the device is full. If the read pointer is not moved after Reset (RS),
the Full Flag (FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536
writes.
EMPTY FLAG ( EF ) — The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer, indicating that
the device is empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF ) — This is a dual-purpose
output. In the single device mode, when Expansion In (XI) is grounded, this output
acts as an indication of a half-full memory.
After half of the memory is filled, and at the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse when the Write
pointer reaches the last location of memory, and an additional XO pulse when the
Read pointer reaches the last location of memory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data.
These outputs are in a high-impedance condition whenever Read (R) is in a HIGH
state.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
CONTROLS:
RESET ( RS ) — Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and write pointers are set
to the first location. A reset is required after power-up before a write operation can
take place. Both the Read Enable (R) and Write Enable (W) inputs must
be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before
the rising edge of RS) and should not change until tRSR after the rising
edge of RS.
WRITE ENABLE ( W ) — A write cycle is initiated on the falling edge of this
input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-
to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM
array sequentially and independently of any on-going read operation.
After half of the memory is filled, and at the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference
between the write pointer and read pointer is less-than or equal to one-half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge
of the last write signal, which inhibits further write operations. Upon the completion
of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a
new valid write to begin. When the FIFO is full, the internal write pointer is blocked
from W, so external changes in W will not affect the FIFO when it is full.
READ ENABLE ( R ) — A read cycle is initiated on the falling edge of the Read
Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on
a First-In/First-Out basis, independent of any ongoing write operations. After Read
Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-
impedance condition until the next Read operation. When all the data has been
read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read
cycle but inhibiting further read operations, with the data outputs remaining in a high-
impedance state. Once a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the
FIFO is empty, the internal read pointer is blocked from R so external changes will
not affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT ( FL/RT ) — This is a dual-purpose input. In
the Depth Expansion Mode, this pin is grounded to indicate that it is the first device
P1-P3P4-P6P7-P9P10-P12P13-P14

7205L12P

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Description:
FIFO 8KX9 ASYNC FIFO
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