APRIL 28, 2016 15 8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
9DBV0841 DATASHEET
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Order Number Shipping Packaging Package Temperature
9DBV0841AKLF Trays 48-pin VFQFPN 0 to +70° C
9DBV0841AKLFT Tape and Reel 48-pin VFQFPN 0 to +70° C
9DBV0841AKILF Trays 48-pin VFQFPN -40 to +85° C
9DBV0841AKILFT Tape and Reel 48-pin VFQFPN -40 to +85° C
Rev. Initiator Issue Date Description Page #
A RDW 8/13/2012
1. Removed "Differential" from DS title and Recommended Application,
corrected typo's in Description. Updated block diagram to show
integrated terminations.
2. Removed references to 60KOhm pulldown under pinout.
3. Updated "Phase Jitter Parameters" table by adding "Industry Limit"
column and updated all Electrical Tables with characterization data.
4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6]
definition.
5. Updated Mark spec with correct part revision (A) and added thermal
data to page 13.
6. Added NDG48 to "Package Outline and Package Dimensions" on page
14 and updated Ordering information to correct part revision (A rev).
7. Move to final
1,2,6-
9,11,13,14
B RDW 2/18/2013
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
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C RDW 8/12/2014
Chan
ed packa
e desi
nator from "MLF" to "VFQFPN" Various
D RDW 3/10/2016
1. Numerous typographical and grammatical updates for document
consistency with other devices in the family, including updated
descriptions for Bytes 0 and 2.
2. Fast and slow slew rates were swapped in the "DIF 0.7V Low Power
HCSL Outputs" table.
3. Changed PCIe clock source from 9FG432 to 9FGV0841/9FGL0841 for
PLL mode phase jitter numbers. New phase jitter numbers are lower.
4. Added epad to pinout diagram and pin descriptions.
5. Updated Clock Input Parameters to be consistent with PCIe Vswing
parameter.
6. Updated package drawing to latest format.
Various
E RDW 4/28/2016
1. Updated max frequency of 100MHz PLL mode to 140MHz
2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
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