74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 12 June 2008 9 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
74AHCT377; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
CP to Qn; see Figure 6
[2]
C
L
= 15 pF - 4.0 9.0 1.0 10.5 1.0 11.5 ns
C
L
= 50 pF - 5.7 10.5 1.0 12.0 1.0 13.5 ns
f
max
maximum
frequency
see Figure 6
C
L
= 15 pF 90 140 - 80 - 80 - MHz
C
L
= 50 pF 85 130 - 75 - 75 - MHz
t
W
pulse width CP HIGH or LOW;
see
Figure 6
5.0 - - 5.0 - 5.0 - ns
t
su
set-up time Dn, E to CP; see Figure 7 4.5 - - 4.5 - 4.5 - ns
t
h
hold time Dn, E to CP; see Figure 7 2.0 - - 2.0 - 2.0 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
= GND to V
CC
[3]
-23- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 °C 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max Min Max
74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 12 June 2008 10 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Clock pulse width, maximum frequency and input to output propagation delays
001aac426
CP input
Qn
output
t
PHL
t
PLH
t
W
V
OH
V
I
GND
V
OL
V
M
V
M
1/f
max
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Data set-up and hold times
mna609
t
h
t
h
t
su
t
su
t
h
t
su
t
W
V
M
V
M
V
M
V
CC
GND
V
CC
GND
V
CC
GND
CP input
Dn input
E input
Table 8. Measurement points
Type Input Output
V
M
V
M
74AHC377 0.5 × V
CC
0.5 × V
CC
74AHCT377 1.5 V 0.5 × V
CC
74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 12 June 2008 11 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Test data is given in Table 9.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 8. Load circuitry for measuring switching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
Table 9. Test data
Type Input Load Test
V
I
t
r
, t
f
C
L
74AHC377 V
CC
3.0 ns 15 pF, 50 pF t
PLH
, t
PHL
74AHCT377 3.0 V 3.0 ns 15 pF, 50 pF t
PLH
, t
PHL

74AHCT377PW,112

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops OCT D-TYPE EDGE
Lifecycle:
New from this manufacturer.
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