74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 12 June 2008 3 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Fig 2. Logic symbol Fig 3. IEC logic symbol
mna918
D0
D1
D2
D3
D4
D5
D6
D7
E
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
mna919
19
16
15
12
9
6
5
11
1C2
1
G1
2D
2
18
17
14
13
8
7
4
3
Fig 4. Logic diagram
mna610
D0
Q0
D
FF1
Q
CP
CP
E
D1
Q1
D
FF2
Q
CP
D2
Q2
D
FF3
Q
CP
D3
Q3
D
FF4
Q
CP
D4
Q4
D
FF5
Q
CP
D5
Q5
D
FF6
Q
CP
D6
Q6
D
FF7
Q
CP
D7
Q7
D
FF8
Q
CP
74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 12 June 2008 4 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SO20 and TSSOP20
377
EV
CC
Q0 Q7
D0 D7
D1 D6
Q1 Q6
Q2 Q5
D2 D5
D3 D4
Q3 Q4
GND CP
mna917
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
E 1 data enable input (active LOW)
Q0 2 flip-flop output
D0 3 data input
D1 4 data input
Q1 5 flip-flop output
Q2 6 flip-flop output
D2 7 data input
D3 8 data input
Q3 9 flip-flop output
GND 10 ground (0 V)
CP 11 clock input (LOW-to-HIGH, edge triggered)
Q4 12 flip-flop output
D4 13 data input
D5 14 data input
Q5 15 flip-flop output
Q6 16 flip-flop output
D6 17 data input
D7 18 data input
Q7 19 flip-flop output
V
CC
20 supply voltage
74AHC_AHCT377_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 12 June 2008 5 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH CP transition;
X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of P
tot
derates linearly at 5.5 mW/K.
Table 3. Function table
[1]
Operating mode Control Input Output
E CP Dn Qn
Load 1 l hH
Load 0 l lL
Hold (do nothing) h X no change
H X X no change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
V
I
input voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V
[1]
20 - mA
I
OK
output clamping current V
O
< 0.5 V or V
O
> V
CC
+ 0.5 V
[1]
20 +20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) 25 +25 mA
I
CC
supply current - +75 mA
I
GND
ground current 75 - mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
[2]
- 500 mW

74AHCT377PW,112

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops OCT D-TYPE EDGE
Lifecycle:
New from this manufacturer.
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