MMA6222EG
Sensors
Freescale Semiconductor 23
Non-acceleration transfers will always succeed except in the case of oscillator fault, SPI error or request error conditions. Only
oscillator failure, SPI error or request error conditions are reported in response to non-acceleration commands. Other error con-
dition are reported as hardware errors in response to acceleration data requests.
4.1.8 Register Write Operations
Register write operations are initiated when bits 15 and 13 from the master is set to a logic ‘0’ and bit 14 is set to a logic ‘1’. Bits
12 through 8 contain a five-bit address, while the last eight bits contain the data value to be written. Only the DEVCTL register is
writable. If an attempt is made to write to any register other than DEVCTL, a request error response (see Figure 4-15) will occur.
Figure 4-9 Register Write Command
Response to a register write operation is illustrated below. DEVCTL bits which can be read as logic ‘1’ (HPFB, ST1 and ST0) will
be indicated during the last eight clock cycles, as shown.
Figure 4-10 Register Write Command Response
4.1.9 Register Read Operations
Register read operations are initiated when bit 15 from the master is set to a logic ‘1’ state and bits 14 and 13 are driven to a logic
low level. The address of the register to be accessed is contained in bits 12 through 8. D
IN
bits 7 through 0 are ignored by
MMA62XXEG during register read command transfers.
Figure 4-11 Register Read Command
Data read from the selected register is returned in bits 7 through 0, as shown below.
Figure 4-12 Register Read Command Response
SCLK
BIT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
IN
1
0
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D00
SCLK
BIT
D
OUT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01
P 0 HPFB 0 ST1
ST0
00
0
1110 0
SCLK
BIT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
IN
0
0
A4 A3 A2 A1 A0 X X X X X X X X1
SCLK
BIT
D
OUT
CS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10
P D4D3D2D1
D0
D6 D5
0
1110 D7
