MMA6222EG
Sensors
30 Freescale Semiconductor
SECTION 5 OPERATING MODES
MMA62XXEG operates in one of two modes, factory test programming mode and normal operating mode. Factory test and pro-
gramming mode is entered only when certain conditions are met, and provides support for programming of customer-defined
data. Normal mode is entered by default when the device is powered on.
5.1 NORMAL OPERATING MODE
Normal mode is entered whenever the device is powered and the V
PP
pin is held at or below the level of V
CC
. In normal mode,
acceleration data and device support data transfers are supported.
5.1.1 Power-On Reset
Upon application of voltage at the V
CC
pin, the internal regulators will begin driving the internal power supply rails. The C
REG
and
C
REGA
pins are tied to the internal rails. As voltages at V
CC
, C
REG
and C
REGA
rise, the device becomes operational. An internal
reset signal is asserted at this time. Separate comparators on monitor all three voltages, and when all are above specified thresh-
olds, the reset signal is negated and the device begins its initialization process.
5.1.2 Device Initialization
Following any reset, the device completes a sequence of operations which initialize internal circuitry. Device initialization is com-
pleted in two phases. During the first phase, the fuse array is read and its contents are transferred to mirror registers. Power to
the fuse array is then removed to reduce supply current load. A voltage reference used within the sensor interface stabilizes dur-
ing the second phase. If the HPFSEL bit is set in the DSP configuration register (DSPCFG), the high-pass filter is also initialized
during phase two.
The device will not respond to SPI accesses during initialization phase one. Acceleration results are not available during initial-
ization phase two, however the SPI is functional and register operations may be performed. If an acceleration data access is
attempted, the device will respond with non-acceleration data.
The first initialization phase requires approximately 800 μs to complete. The second phase completes in approximately 3 ms if
no high-pass filter is selected, and 200 ms if the HPFSEL bit is programmed to a logic ‘1’ state. The DEVINIT bit in the device
status register (DEVSTAT) remains set following reset until the second phase of device initialization completes.