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SST25WF020AT-40I/NP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
SST25WF020A
DS20005139E-page 10 2014 Microchip Technology Inc.
5.1 Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs a data stream starting from
the specified address location. The data stream is con-
tinuous through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer automatically incre-
ments to the beginning (wrap-around) of the address
space. For example, for 2 Mbit density, once the data
from the address location 3FFFFH is read, the next out-
put is from address location 000000H. The Read
instruction is initiated by executing an 8-bit command,
03H, followed by address bits A
23
-A
0
. CE# must
remain active low for the duration of the Read cycle.
See Figure 5-1 for the Read sequence.
FIGURE 5-1: READ SEQUENCE
5.2 High-Speed-Read (40 MHz)
The High-Speed-Read instruction supporting up to 40
MHz Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A
23
-A
0
] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 5-2 for the High-
Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. For example, for 2 Mbit density, once the data
from address location 3FFFFH is read, the next output
will be from address location 000000H.
FIGURE 5-2: HIGH-SPEED-READ SEQUENCE
2513 F06.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16
23
24
31
32
3
40
7047 48 55 56 63 64
N+2 N+3 N+4N N+1
D
OUT
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
2513 F07.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 3 40
47 48 55 56 63 64
N+2 N+3 N+4
N
N+1
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
MSB
2014 Microchip Technology Inc. DS20005139E-page 11
SST25WF020A
5.3 Page-Program
The Page-Program instruction programs up to 256
Bytes of data in the memory. The data for the selected
page address must be in the erased state (FFH) before
initiating the Page-Program operation. A Page-Pro-
gram applied to a protected memory area will be
ignored. Prior to the program operation, execute the
WREN instruction.
To execute a Page-Program operation, the host drives
CE# low, then sends the Page-Program command
cycle (02H), three address cycles, followed by the data
to be programmed, and then drives CE# high. The pro-
grammed data must be between 1 to 256 Bytes and in
whole byte increments; sending less than a full byte will
cause the partial byte to be ignored. Poll the BUSY bit
in the Status register, or wait T
PP
, for the completion of
the internal, self-timed, Page-Program operation. See
Figure 5-3 for the Page-Program sequence and Figure
6-9 for the Page-Program flow chart.
When executing Page-Program, the memory range for
the SST25WF020A is divided into 256-Byte page
boundaries. The device handles the shifting of more
than 256 Bytes of data by maintaining the last 256
Bytes as the correct data to be programmed. If the tar-
get address for the Page-Program instruction is not the
beginning of the page boundary (A[7:0] are not all
zero), and the number of bytes of data input exceeds or
overlaps the end of the address of the page boundary,
the excess data inputs wrap around and will be pro-
grammed at the start of that target page.
FIGURE 5-3: PAGE-PROGRAM SEQUENCE
25139 F60.1
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. Data Byte 0
02
HIGH IMPEDANCE
15 16
23 24
31
32
39
MODE 0
MODE 3
MSBMSB
MSB
LSB
CE#(cont’)
SO(cont’)
SI(cont’)
SCK(cont’)
40 41 42 43 44 45 46 47 48
Data Byte 1
HIGH IMPEDANCE
MSBMSB
MSB
LSB
50 51 52 53 54 55
2072
49
Data Byte 2
2073
2074
2075
2076
2077
2078
2079
Data Byte 255
LSBLSB
LSB
LSB
SST25WF020A
DS20005139E-page 12 2014 Microchip Technology Inc.
5.4 Sector-Erase
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H or D7H, followed by
address bits [A
23
-A
0
]. Address bits [A
MS
-A
12
]
(A
MS
= Most Significant address) are used to deter-
mine the sector address (SA
X
), remaining address bits
can be V
IL
or V
IH.
CE# must be driven high before the
instruction is executed. Poll the BUSY bit in the Soft-
ware Status register, or wait T
SE
, for the completion of
the internal self-timed Sector-Erase cycle. See Figure
5-4 for the Sector-Erase sequence and Figure 6-9 for
the flow chart.
FIGURE 5-4: SECTOR-ERASE SEQUENCE
5.5 64-KByte Block-Erase
The 64-KByte Block-Erase instruction clears all bits in
the selected 64 KByte block to FFH. Applying this
instruction to a protected memory area results in the
instruction being ignored. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of any com-
mand sequence.
Initiate the 64-Byte Block-Erase instruction by execut-
ing an 8-bit command, D8H, followed by address bits
[A
23
-A
0
]. Address bits [A
MS
-A
16
] (A
MS
= Most Signifi-
cant Address) determine the block address (BA
X
),
remaining address bits can be V
IL
or V
IH.
CE# must be
driven high before executing the instruction. Poll the Busy bit
in the software status register or wait T
BE
for the com-
pletion of the internal self-timed Block-Erase cycle. See
Figure 5-5 for the 64-KByte Block-Erase sequences
and Figure 6-9 for the flow chart.
FIGURE 5-5: 64-KBYTE BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
20 or D7
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
253 F13.0
MSBMSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
2513 F15.0
MSB MSB
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

SST25WF020AT-40I/NP

Mfr. #:
Buy SST25WF020AT-40I/NP
Manufacturer:
Microchip Technology
Description:
NOR Flash 1.65V to 1.95V 2Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
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