P82B715_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 9 November 2009 14 of 23
NXP Semiconductors
P82B715
I
2
C-bus extender
[1] Operation with reduced performance is possible down to 3 V. Typical static sinking performance is not degraded at 3 V, but the dynamic
sink currents while the output is being driven through 0.5V
CC
are reduced and can increase fall times. Timing-critical designs should
accommodate the guaranteed minimums.
[2] Buffer is passive in this test. The Sx/Sy sink current flows via an internal resistor to the driver connected at the Lx/Ly I/O.
[3] A conventional input-output delay will not be observed in the Sx/Lx voltage waveforms because the input and output pins are internally
tied with a 30 Ω resistor so they show equal logic voltage levels, to within 100 mV. When connected in an I
2
C-bus system, an Sx/Sy
input pin cannot rise/fall until the buffered bus load at the output pin has been driven by the internal amplifier. This test measures the bus
propagation delay caused to falling or rising voltages at the Lx/Ly output (as well as the Sx/Sy input) by the amplifier’s response time.
The figure given is measured with a drive current as shown in Figure 12. Because this is a dynamic bus test in which a corresponding
bus driving IC has an output voltage well above 0.4 V, 6 mA is used instead of the static 3 mA.
[4] The signal path Lx to Sx and Ly to Sy is passive via the internal 30 Ω resistor. There is no amplifier involved and essentially no signal
propagation delay.
11. Test information
Input currents
I
Sx
, I
Sy
input current from I
2
C-bus I
Lx
, I
Ly
sink on buffered bus = 30 mA - - −3mA
I
Lx
, I
Ly
input current from buffered bus V
CC
>3V; I
Sx
, I
Sy
sink on
I
2
C-bus = 3 mA
[2]
--−3mA
I
Lx
, I
Ly
leakage current on buffered bus V
CC
= 3 V to 12 V; V
Lx
, V
Ly
=V
CC
and
V
Sx
, V
Sy
=V
CC
- - 200 µA
Impedance transformation
Z
in
/Z
out
input/output impedance V
Sx
<V
Lx
and the buffer is active;
I
Lx
sinking 30 mA on buffered bus
81013
Buffer delay times
t
rise/fall delay
I
Sx
to V
Lx
I
Sy
to V
Ly
time delay to V
Lx
voltage
crossing 0.5V
CC
for input drive
current step I
Sx
at Sx
see
Figure 12; R
Lx
pull-up = 270 Ω;
no capacitive load; V
CC
=5V
[3]
- 250 - ns
t
rise/fall delay
V
Lx
to V
Sx
V
Ly
to V
Sy
buffer time delay of switching
edges between V
Lx
input and
V
Sx
output
R
Sx
pull-up = 4700 Ω;
no capacitive load; V
CC
=5V
[4]
-0-ns
Table 5. Characteristics
…continued
T
amb
=25
°
C; V
CC
= 5 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Fig 12. Test circuit for delay times
I = 6 mA
002aad693
P82B715
input
Sx Lx
4.7 kΩ
5 V
270 Ω
P82B715
Lx Sx
4.7 kΩ
V V V
input
current
t
delay
t
delay
0 V
5 V
input and
output
voltage
output
