P82B715TD,118 Datasheet P82B715TD,118, P82B715TD,112, P82B715PN,112 | P4-P6

Product data sheet Rev. 08 — 9 November 2009 4 of 23

NXP Semiconductors

P82B715

C-bus extender

7. Functional description

The P82B715 is a dual bidirectional logic signal device having unity voltage gain in both

directions, but ×10 current ampliﬁcation in one direction that allows increasing the

allowable I

C-bus system capacitance. It contains identical circuits for each I

C-bus signal

and requires no external directional control. It uses unidirectional analog current

ampliﬁcation to increase the current sink capability of I

C-bus chips by a factor of 10 and

to change the I

C-bus speciﬁcation limit of 400 pF to a 4 nF system limit. This allows

C-bus, or similar bus systems, to be extended over long distances using conventional

cables and without degradation of system performance.

P82B715 provides current ampliﬁcation from its I

C-bus to its low-impedance or buffered

bus. Whenever current is ﬂowing out of Sx, into an I

C-bus chip driving the I

C-bus LOW,

P82B715 will sink ten times that current into Lx to drive the buffered bus LOW (see

Figure 4).

To minimize interference and ensure stability, the current rise and fall times of the Lx drive

ampliﬁer are internally controlled.

The P82B715 does not amplify signal currents ﬂowing in the other direction, i.e., into Sx

from the I

C-bus. The Sx pin is driven LOW by current ﬂowing out of Lx to the driver of that

buffered side.

The buffered bus logic LOW voltage at Lx simply drives the I

C-bus at Sx LOW via the

internal 30 Ω resistor. The buffer’s offset voltage (the difference between Sx and Lx)

depends on the current ﬂowing in the sense resistor so it will be very small when the bus

currents are small, but it is guaranteed not to exceed 100 mV in either direction with full

static I

C-bus loading.

The unity voltage gain, with signal current ampliﬁcation dependent on direction, preserves

the multi-master, bidirectional, open-collector/open-drain, characteristic of any connected

C-bus lines and provides these characteristics to the new low-impedance bus. Bus logic

signal voltage levels will be clamped at (V

+ 0.7 V), but otherwise are independent of

the supply voltage V

7.1 Sx, Sy: I

C-bus SDA or SCL

On the normal side, because the two buffer circuits in the P82B715 are identical, either

the Sx or Sy input pins can be used as the I

C-bus SDA data line, or the SCL clock line.

Fig 4. Equivalent circuit: one-half P82B715

002aad688

Lx buffered bus

= 10 × I

9 × I

CURRENT

SENSE

GND

C-bus Sx

= I

30 Ω

Product data sheet Rev. 08 — 9 November 2009 5 of 23

NXP Semiconductors

P82B715

C-bus extender

7.2 Lx, Ly: buffered bus LDA or LCL

On the special low-impedance or buffered line side, the corresponding output at the Lx or

Ly pins becomes the LDA data line or LCL clock line.

7.3 V

, GND: positive and negative supply pins

The power supply voltages at each P82B715 used in a system are normally nominally the

same. If they differ by a signiﬁcant amount, noise margin may be sacriﬁced as the bus

HIGH level should not exceed the lowest of those supplies.

8. Application design-in information

By using two (or more) P82B715 ICs, a sub-system can be built that retains the interface

characteristics of a normal I

C-bus device so that the sub-system may be included in, or

added onto, any I

C-bus or related system.

The sub-system shown in Figure 5 features a low-impedance or buffered bus, capable of

driving large wiring capacitance.

The P82B715 will operate with a supply voltage from 3 V to 12.5 V but the logic signal

levels at Sx/Lx are independent of the chip’s supply. They remain at the levels presented

to the chip by the attached ICs. The maximum static I

C-bus sink current, 3 mA, ﬂowing in

either direction in the internal current sense resistor, causes a difference, or offset voltage,

less than 100 mV between the bus logic LOW levels at Sx and Lx. This makes P82B715

fully compatible with all logic signal drivers, including TTL. The P82B715 cannot modify

the bus logic signal voltage levels but it contains internal diodes connected between Lx/Sx

and V

that will conduct and limit the logic signal swing if the applied logic levels would

have exceeded the supply voltage by more than 0.7 V. In normal applications external

pull-up resistors will pull the connected buses up to the desired voltage HIGH level.

Usually this will be the chip supply, V

, but for very low logic voltages it is necessary to

use a V

of at least 3.3 V and preferably even higher. Note that full performance over

temperature is only guaranteed from 4.5 V. Speciﬁcation de-ratings apply when its supply

voltage is reduced below 4.5 V. The absolute minimum V

is 3 V.

Fig 5. Minimum sub-system with P82B715

002aad690

1/2

P82B715

standard

C-bus

SDA

SCL

special

buffered bus

long

cable

1/2

P82B715

SDA

SCL

special

buffered bus

standard

C-bus

C-BUS

DEVICE

LDA

LCL

Product data sheet Rev. 08 — 9 November 2009 6 of 23

NXP Semiconductors

P82B715

C-bus extender

8.1 I

C-bus systems

As in standard I

C-bus systems, pull-up resistors are required to provide the logic HIGH

levels on the buffered bus. (The standard open-collector conﬁguration is retained.) The

value and number of pull-up resistors used is ﬂexible and depends on the system

requirements and designer preferences.

If P82B715 ICs are to be permanently connected into a system it could be conﬁgured with

only one pull-up resistor on the buffered bus and none on the I

C-buses, but the system

design will be simpliﬁed, and performance improved, by ﬁtting separate pull-ups on each

section of the bus. When a sub-system using P82B715 may be optionally connected to an

existing I

C-bus system that already has a pull-up, then the effects of the sub-system

pull-ups acting in parallel with the existing I

C-bus pull-up must be considered.

8.1.1 Pull-up resistance calculation

When calculating the pull-up resistance values, the gain of the buffer introduces scaling

factors which must be applied to the system components. In practical systems the pull-up

resistance value is usually calculated to achieve the rise time requirement of the system.

As an approximation, this requirement will be satisﬁed for a standard 100 kHz system if

the time constant of the total system (product of the net resistance and net capacitance) is

set to 1 microsecond or less.

In systems using P82B715s, the most convenient way to achieve the total system

rise time requirement is by considering each bus node separately. Each of the I

C-bus

nodes, and the buffered bus node, is designed by selecting its pull-up resistor to provide

the required rise time by setting its time constant (product of the pull-up resistance and

load capacitance) equal to the I

C-bus rise time requirement. If each node complies, then

the system requirement will also be met with a small safety margin.

This arrangement, using multiple pull-ups as in Figure 6, provides the best system

performance and allows stand-alone operation of individual I

C-buses if parts of the

extended system are disconnected or re-connected. For each bus section the pull-up

resistor for a Standard-mode system is calculated as shown in Equation 1:

(1)

Where: C device = sum of any connected device capacitances, and C wiring = total wiring

and stray capacitance on the bus section.

Remark: The 1 µs is an approximation, with a safety factor, to the theoretical

time-constant necessary to meet the Standard-mode 1 µs bus rise time speciﬁcation in a

system with variable logic thresholds where the CMOS limits of 30 % and 70 % of V

apply. The actual RC requirement can be shown to be 1.18 µs. For a Fast-mode system,

and the same safety margin, replace the 1 µs with its 300 ns requirement.

If these capacitances cannot be measured or calculated then an approximation can be

made by assuming that each device presents 10 pF of load capacitance and 10 pF of

trace capacitance and that cables range from 50 pF to 100 pF per meter.

If only a single pull-up must be used then it must be placed on the buffered bus (as R2 in

Figure 6) and the associated total system capacitance calculated by combining the

individual bus capacitances into an equivalent capacitive loading on the buffered bus.

1 µs

C device C wiring+

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P82B715TD,118

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Interface - Signal Buffers, Repeaters I2C BUS EXTENDER

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P82B715TD,118

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