LT3508
16
3508fd
APPLICATIONS INFORMATION
TRACK/SS1
(8a)
LT3508
20ms/DIV
V
OUT1
1V/DIV
20ms/DIV
1V/DIV
20ms/DIV
1V/DIV
V
OUT2
TRACK/SS2
0.1µF
0.047µF
3.3V
5V
TRACK/SS1
(8b)
LT3508
V
OUT1
V
OUT2
TRACK/SS2
0.22µF
3.3V
5V
TRACK/SS1
(8e)
LT3508
V
OUT1
V
OUT2
TRACK/SS2
3.3V
5V
R1
28.7k
R2
10.0k
Independent Start-Up Ratiometric Start-Up
Coincident Start-Up
TRACK/SS1
(8d)
LT3508
V
OUT1
PG1
V
OUT2
TRACK/SS2
0.1µF
0.047µF
3.3V
5V
EXTERNAL
SOURCE
Output Sequencing
Controlled Power Up and Down
+
TRACK/SS1
(8c)
LT3508
V
OUT1
V
OUT2
TRACK/SS2
0.1µF
3.3V
5V
R1
28.7k
R2
10.0k
V
OUT1
V
OUT1
V
OUT2
V
OUT2
V
OUT1
V
OUT2
20ms/DIV
1V/DIV
20ms/DIV
1V/DIV
V
OUT1
V
OUT2
V
OUT1
V
OUT2
EXTERNAL SOURCE
Figure 8
Output Tracking and Sequencing
Complex output tracking and sequencing between channels
can be implemented using the LT3508’s TRACK/SS and
PG pins. Figure 8 shows several confi gurations for output
tracking and sequencing of 5V and 3.3V applications.
Independent soft-start for each channel is shown in Fig-
ure 8a. The output ramp time for each channel is set by the
soft-start capacitor as described in the soft-start section.
LT3508
17
3508fd
Ratiometric tracking is achieved in Figure 8b by connecting
both the TRACK/SS pins together. In this confi guration the
TRACK/SS pin source current is doubled (2.4A) which
must be taken into account when calculating the output
rise time.
Do not tie TRACK/SS1 and TRACK/SS2 together if using
multiple inputs. If V
IN2
is below 3V, TRACK/SS2 pulls low
and would hold TRACK/SS1 low as well if the two pins
are tied together, which would prevent channel 1 from
operating.
By connecting a feedback network from V
OUT1
to the
TRACK/SS2 pin with the same ratio that set the V
OUT2
voltage, absolute tracking shown in Figure 8c is imple-
mented. A small V
OUT2
voltage offset will be present due
to the TRACK/SS2 1.2A source current. This offset can
be corrected for by slightly reducing the value of R2. Use
a resistor divider such that when V
OUT1
is in regulation,
TRACK/SS2 is pulled up to 1V or greater. If TRACK/SS is
below 1V, the output may regulate FB to a voltage lower
than the 800mV reference voltage.
Figure 8d illustrates output sequencing. When V
OUT1
is
within 10% of its regulated voltage, PG1 releases the
TRACK/SS2 soft-start pin allowing V
OUT2
to soft-start.
In this case PG1 will be pulled up to 1.3V by the TRACK/
SS pin.
If precise output ramp up and down is required, drive the
TRACK/SS pins as shown in Figure 8e.
Multiple Inputs
For applications requiring large inductors due to high V
IN
to V
OUT
ratios, a 2-stage step down approach may reduce
inductor size by allowing an increase in frequency. A dual
step-down application (Figure 9) steps down the input
voltage (V
IN1
) to the highest output voltage, then uses that
voltage to power the second output (V
IN2
). V
OUT1
must
be able to provide enough current for its output plus the
input current at V
IN2
when V
OUT2
is at its maximum load.
For applications with multiple input voltages, the LT3508
can accommodate input voltages as low as 3V on V
IN2
.
This can be useful in applications regulating outputs from
a PCI Express bus, where the 12V input is power limited
and the 3.3V input has power available to drive other
outputs. In this case, tie the 12V input to V
IN1
and the
3.3V input to V
IN2
. See the Typical Application section for
an example circuit.
Shorted and Reverse Input Protection
If the inductor is chosen so that it won’t saturate exces-
sively, an LT3508 step-down regulator will tolerate a shorted
output. There is another situation to consider in systems
where the output will be held high when the input to the
APPLICATIONS INFORMATION
Figure 9. 1MHz, Wide Input Range 5V and 1.8V Outputs
V
IN
5.7V TO 36V
BOOST2
LT3508
V
IN1
V
IN2
GND
3508 F09
RT/SYNC
C7
330pF
C5
47µF
C4
10µF
C1
4.7µF
C2
0.1µF
C3
0.1µF
R6
47k
C6
100pF
R5
39k
R4
15.0k
R8
33.2k
f
SW
= 1MHz
R1
56.2k
R7
100k
R2
18.7k
R3
10.7k
L2
3.3µH
L1 6.8µH
D1
D2
OUT1
D3 D4
POWER
GOOD
OUT2
1.8V
1A
OUT1
5V
0.9A
C8
1nF
C9
3.3nF
BOOST1
SHDN
SW2
SW1
FB2FB1
V
C2
PG1
V
C1
TRACK/SS1
PG2TRACK/SS2
ON OFF
LT3508
18
3508fd
LT3508 is absent. This may occur in battery charging
applications or in battery back-up systems where a battery
or some other supply is diode OR-ed with the LT3508’s
output. If the V
IN
pin is allowed to fl oat and the SHDN pin
is held high (either by a logic signal or because it is tied
to V
IN
), then the LT3508’s internal circuitry will pull its
quiescent current through its SW pin. This is fi ne if your
system can tolerate a few mA in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the V
IN
pin is grounded while the output
is held high, then parasitic diodes inside the LT3508 can
pull large currents from the output through the SW pin
and the V
IN
pin. Figure 10 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
APPLICATIONS INFORMATION
Figure 11. A Good PCB Layout Ensures Proper Low EMI Operation
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 11 shows the
recommended PCB layout with trace and via locations. Note
that large, switched currents fl ow in the LT3508’s V
IN
and
SW pins, the catch diode (D1) and the input capacitor (C
IN
).
The loop formed by these components should be as small
as possible. These components, along with the inductor
and output capacitor, should be placed on the same side
of the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The SW and BOOST nodes should be
as small as possible. Finally, keep the FB and V
C
nodes
small so that the ground traces will shield them from the
SW and BOOST nodes. The exposed pad on the bottom of
the package must be soldered to ground so that the pad
acts as a heat sink. To keep thermal resistance low, extend
the ground plane as much as possible, and add thermal
vias under and near the LT3508 to additional ground planes
within the circuit board and on the bottom side.
V
IN
V
IN
V
OUT
SW
LT3508
D4
PARASITIC DIODE
3508 F10
Figure 10. Diode D4 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output
(11a) Example Layout for FE16 Package (11b) Example Layout for QFN Package

LT3508HFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Monolithic 1.4A Step-Down Switching Regulator
Lifecycle:
New from this manufacturer.
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