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SI5018-B-GMR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Rev. 1.3 6/08 Copyright © 2008 by Silicon Laboratories Si5018
Si5018
SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC
Features
Complete high-speed, low-power, CDR solution includes the following:
Applications
Description
The Si5018 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/STM-16 data
rates. In addition, support for 2.7 Gbps data streams is also provided for
applications that employ forward error correction (FEC). DSPLL™
technology eliminates sensitive noise entry points thus making the PLL
less susceptible to board-level interaction and helping to ensure optimal
jitter performance.
The Si5018 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Supports OC-48 /STM-16 & FEC
Low power—270 mW
(typ OC-48)
Small footprint: 4x4 mm
DSPLL™ Eliminates external
loop filter components
3.3 V tolerant control inputs
Exceeds all SONET/SDH jitter
specifications
Jitter generation
3.0 mUI
rms
(typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V Supply
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Board level serial links
DSPLL
TM
Phase-Locked
Loop
Retimer
BUF
BUF
BUF
DIN +
DIN –
REXT
LOL
2
REFCLKIN +
REFCLKIN –
2
DOUT +
DOUT –
CLKOUT +
CLKOUT –
PWRDN/CAL
2
2
Bias
Ordering Information:
See page 17.
Pin Assignments
Si5018
GND
Pad
Connection
15
14
13
12
11
PWRDN/CA
L
DOUT+
VDD
DOUT–
VDD
1
2
3
4
5
VDD
GND
R
EFCLK–
REXT
R
EFCLK+
20 19 18 17 16
GND
GND
CLKOUT–
CLKOUT+
GND
6 7 8 9 10
LOL
GND
DIN+
DIN–
VDD
Si5018
2 Rev. 1.3
Si5018
Rev. 1.3 3
TABLE OF CONTENTS
Section Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

SI5018-B-GMR

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Buy SI5018-B-GMR
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products
Lifecycle:
New from this manufacturer.
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