Si5018
Rev. 1.3 7
Table 3. AC Characteristics (Clock and Data)
(V
A
2.5 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Clock Rate f
CLK
2.4 — 2.7 GHz
Output Rise/Fall Time t
R,
t
F
Figure 3 — 80 110 ps
Clock to Data Delay
FEC (2.7 GHz)
OC-48
t
C-D
Figure 2
225
225
250
250
270
270
ps
Input Return Loss 100 kHz–2.5 GHz
2.5 GHz–4.0 GHz
—
—
16
13
—
—
dB
dB
Table 4. AC Characteristics (PLL Characteristics)
(V
A
2.5 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Tolerance* J
TOL(P–P)
f=600Hz 40 — — UI
PP
f = 6000 Hz 4 — — UI
PP
f=100kHz 4 — — UI
PP
f = 1 MHz .4 — — UI
PP
RMS Jitter Generation
*
J
GEN(rms)
with no jitter on serial data — 2.9 5.0 mUI
Peak-to-Peak Jitter Generation
*
J
GEN(PP)
with no jitter on serial data — 25 55 mUI
Jitter Transfer Bandwidth
*
J
BW
——2.0MHz
Jitter Transfer Peaking
*
J
P
—0.030.1dB
Acquisition Time T
AQ
After falling edge of
PWRDN/CAL
1.45 1.5 1.7 ms
From the return of valid data 40 60 150 μs
Input Reference Clock Duty
Cycle
C
DUTY
40 50 60 %
Input Reference Clock Frequency
Tolerance
C
TOL
–100 — 100 ppm
Reference Clock Range 19.44 — 168.75 MHz
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
LOL 450 600 750 ppm
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
LOCK 150 300 450 ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 2
23
– 1 data pattern.
