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IPS022G

P1-P3P4-P6P7-P9P10-P10
IPS022G
4 www.irf.com
Symbol Parameter Min. Typ. Max. Units Test Conditions
T
sd
Over temperature threshold — 165 —
o
C See fig. 1
I
sd
Over current threshold 4 5.5 7 A See fig. 1
V
reset
IN protection reset threshold 1.5 2.3 3 V
T
reset
Time to reset protection
2
10
40
µs V
in
= 0V, Tj = 25
o
C
EOI_OT Short circuit energy (see application note)
—
400
—
µJV
cc
= 14V
Protection Characteristics
Lead Assignments
Part Number
8 Lead SOIC
(Dual)
IPS022G
Functional Block Diagram
All values are typical
IN
DRAIN
SOURCE
8.1 V
80
µ
A
47 V
I sense
200 k
Ω
1000
Ω
S Q
R
Q
T > 165°c
I > Isd
1
S1 In1 S2 In2
D1 D1 D2 D2
IPS022G
www.irf.com 5
Figure 1 - Timing diagram
Tr-in
10 %
90 %
90 %
10 %
Td on
Td off
tf
tr
Ids
Tr-in
Vin
Vds
Figure 2 - IN rise time & switching time definitions
Tsd
(165 °c)
Vin
Ids
Isd
I shutdown
T
T shutdown
t < T reset
t > T reset
5 V
0 V
14 V
IN
D
S
5 v
0 v
L
R
+
-
Vds
Ids
Vin
V load
Rem : V load is negative
during demagnetization
Figure 4 - Active clamp test circuit
Vds
Vin
T clam
p
Vds clam
p
(
Vcc
)
( see Appl . Notes to evaluate power dissipation )
Figure 3 - Active clamp waveforms
IPS022G
6 www.irf.com
All curves are typical values with standard footprints. Operating in the shaded area is not recommended.
Figure 6 - Normalized Rds(on) (%) Vs Tj (
o
C)Figure 5 - Rds ON (mΩ) Vs Input Voltage (V)
Tj = 150
o
C
Tj = 25
o
C
0
50
100
150
200
250
300
012345678
0%
20%
40%
60%
80%
100%
120%
140%
160%
180%
200%
-50 -25 0 25 50 75 100 125 150 175
Figure 8 - Turn-OFF Delay Time & Fall Time (us)
Vs Input Voltage (V)
Figure 7 - Turn-ON Delay Time, Rise Time & Time
to 130% final Rds
(on)
(us) Vs Input Voltage (V)
0
1
2
3
4
5
6
7
8
9
10
012345678
ton delay
rise time
130% rdson
0
1
2
3
4
012345678
toff delay
fall time
P1-P3P4-P6P7-P9P10-P10

IPS022G

Mfr. #:
Buy IPS022G
Manufacturer:
Infineon / IR
Description:
Gate Drivers IPS Dual Ch Low Side Driver
Lifecycle:
New from this manufacturer.
Delivery:
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