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CY7C4265V-15ASC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06012 Rev. *A Revised December 26, 2002
285V
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— I
CC
= 30 mA
— I
SB
= 4 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• Retransmit function
• Output Enable (OE
) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin 10x10 STQFP
• Pin-compatible density upgrade to CY7C42X5V-ASC
families
• Pin-compatible 3.3V solutions for CY7C4255/65/75/85
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
the CY7C42X5V Synchronous FIFO family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN
).
When WEN
is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN
). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE
). The read and write clocks may be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI
,
RXI
), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO
and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI
and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be tied to V
CC
.
Q
0 – 17
4275V–1
THREE-ST ATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0 – 17
REN
RCLK
FF
EF
PAE
WENWCLK
RS
FL/RT
WXI
OE
PAF
WXO/HF
RXI
RXO
SMODE
Logic Block Diagram
High
Density
Dual-Port
RAM Array
8Kx9
32Kx9
16Kx9
64Kx9
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document #: 38-06012 Rev. *A Page 2 of 20
Functional Description (continued)
The CY7C4255/65/75/85V provides five status pins. These
pins are decoded to determine one of five states: Empty, Al-
most Empty, Half Full, Almost Full, and Full (see Table 2). The
Half Full flag shares the WXO
pin. This flag is valid in the
stand-alone and width-expansion configurations. In the depth
expansion, this pin provides the expansion out (WXO
) infor-
mation that is used to signal the next FIFO when it will be
activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the V
CC
/SMODE is tied to V
SS
. All
configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Pin Configuration
EF
STQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
16
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
15
Q
15
GND
Q
16
Q
17
GND
V
CC
RS
OE
LD
REN
RCLK
GND
D
17
D
16
PAE
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
XO/HF
RXO
Q
0
Q
1
GND
Q
2
Q
3
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
V
CC
/SMODE
FL/RT
4275V–3
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
Selection Guide
7C4255/65/75/85V-10 7C4255/65/75/85V-15 7C4255/65/75/85V-25
Maximum Frequency (MHz) 100 66.7 40
Maximum Access Time (ns) 8 10 15
Minimum Cycle Time (ns) 10 15 25
Minimum Data or Enable Set-Up (ns) 3.5 4 6
Minimum Data or Enable Hold (ns) 0 0 1
Maximum Flag Delay (ns) 8 10 15
Active Power Supply
Current (I
CC1
) (mA)
Commercial 30 30 30
Industrial 35
CY7C4255V CY7C4265V CY7C4275V CY7C4285V
Density 8K x 18 16K x 18 32K x 18 64K x 18
Package 64-pin 10x10 TQFP 64-pin 10x10 TQFP 64-pin 10x10 TQFP 64-pin 10x10 TQFP
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document #: 38-06012 Rev. *A Page 3 of 20
Pin Definitions
Signal Name Description I/O Function
D
0–17
Data Inputs I Data inputs for an 18-bit bus.
Q
0–17
Data Outputs O Data outputs for an 18-bit bus.
WEN Write Enable I Enables the WCLK input.
REN Read Enable I Enables the RCLK input.
WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD
is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD
is asserted, RCLK reads data out of the programmable flag-
offset register.
WXO/HF Write Expansion
Out/Half Full Flag
O Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI
of next device.
EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE
is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
PAF Programmable
Almost Full
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF
is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
LD Load I When LD is LOW, D
0–17
(Q
0–17
) are written (read) into (from) the programmable-
flag-offset register.
FL/RT First Load/
Retransmit
I Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL
tied to V
SS
; all other
devices will have FL
tied to V
CC
. In standard mode or width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded – Tied to V
SS
. Retransmit function is also available in stand-alone
mode by strobing RT.
WXI Write Expansion
Input
I Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
SS
.
RXI Read Expansion
Input
I Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
SS
.
RXO Read Expansion
Output
O Cascaded – Connected to RXI of next device.
RS Reset I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE
is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
V
CC
/SMODE Synchronous
Almost Empty/
Almost Full Flags
I Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to V
CC
.
Synchronous Almost Empty/Almost Full flags – tied to V
SS
.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

CY7C4265V-15ASC

Mfr. #:
Buy CY7C4265V-15ASC
Manufacturer:
Cypress Semiconductor
Description:
IC FIFO 16KX18 SYNCHRONOUS 64QFP
Lifecycle:
New from this manufacturer.
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