CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document #: 38-06012 Rev. *A Page 16 of 20
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS
cycle. A HIGH pulse on RT resets the
internal read pointer to the first physical location of the FIFO.
WCLK and RCLK may be free running but must be disabled
during and t
RTR
after the retransmit pulse. With every valid
read cycle after retransmit, previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
cycle. Data written to the FIFO after activation of RT are trans-
mitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
The CY7C4255/65/75/85V can be expanded in width to pro-
vide word widths greater than 18 in increments of 18. During
width expansion mode all control line inputs are common and
all flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO; the PAE
and PAF
flags can be detected from any one device. This technique will
avoid reading data from, or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK. Figure 1 demonstrates a 36-word
width by using two CY7C4255/65/75/85Vs.
Table 2. Flag Truth Table
Number of Words in FIFO
FF
PA
F HF
PA
E EF7C4255V – 8K x 18 7C4265V – 16K x 18 7C4275V – 32K x 18 7C4285V – 64K x 18
0 0 0 0 H H H L L
1 to n
[36]
1 to n
[36]
1 to n
[36]
1 to n
[36]
H H H L H
(n+1) to 4096 (n+1) to 8192 (n+1) to 16384 (n+1) to 32768 H H H H H
4097 to (8192–(m+1)) 8193 to (16384
–(m+1))
16385 to
(32768–(m+1))
32769 to (65536
–(m+1))
H H L H H
(8192–m)
[37]
to 8192 (16384–m)
[37]
to
16384
(32768–m)
[37]
to
32767
(65536–m)
[37]
to
65535
H L L H H
8192 16384 32768 65536 L L L H H
Figure 1. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory Used in a Width Expansion
Configuration
Notes:
36. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
37. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
4275V–24
FF
FF EF
EF
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN
)
LOAD (LD)
PROGRAMMABLE(PAE
)
HALF FULL FLAG (HF
)
FULL FLAG (FF)
7C4255V
7C4265V
1836
DATA IN (D)
RESET
(RS)
18
RESET(RS)
READ CLOCK (RCLK)
READ ENABLE (REN
)
OUTPUT ENABLE (OE
)
PROGRAMMABLE (PAF)
EMPTY FLAG
(EF)
18
DATA OUT (Q)
18 36
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
7C4275V
7C4285V
7C4255V
7C4265V
7C4275V
7C4285V
