Philips Semiconductors Product specification
TrenchMOS transistor BUK7605-30A
Standard level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope V
DS
Drain-source voltage 30 V
suitable for surface mounting. Using I
D
Drain current (DC) 75 A
’trench’ technology the device P
tot
Total power dissipation 230 W
features very low on-state T
j
Junction temperature 175 ˚C
resistance. It is intended for use in R
DS(ON)
Drain-source on-state 5 mΩ
automotive and general purpose resistance V
GS
= 10 V
switching applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
(no connection possible)
3 source
mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 30 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -30V
±V
GS
Gate-source voltage - - 20 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 75 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 75 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 400 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 230 W
T
stg
, T
j
Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 0.65 K/W
mounting base
R
th j-a
Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient board
d
g
s
13
mb
2
August 1999 1 Rev 1.100