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LTC4269IDKD-2#TRPBF

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LTC4269-2
22
42692fb
An increase of voltage at the SD_V
SEC
pin causes the
maximum duty cycle clamp to decrease. If SD_V
SEC
is
resistively divided down from power supply input volt-
age, a volt-second clamp is realized. To adjust the initial
maximum duty cycle clamp, the SS_MAXDC pin voltage
is programmed by a resistor divider from the 2.5V V
REF
pin to GND. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
Soft-Start
The LTC4269-2 provides true PWM soft-start by using the
SS_MAXDC pin to control soft-start timing. The propor-
tional relationship between SS_MAXDC voltage and switch
maximum duty cycle clamp allows the SS_MAXDC pin
to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
A soft-start event is triggered whenever V
IN
is too low,
SD_V
SEC
is too low (power supply UVLO), or a 107mV
overcurrent threshold at OC pin is exceeded. Whenever a
soft-start event is triggered, switching at SOUT and OUT
is stopped immediately.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below its reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to GND on the
SS_MAXDC pin in combination with a resistor divider from
V
REF
, defines the soft-start timing.
Current Mode Topology (I
SENSE
Pin)
The LTC4269-2 current mode topology eases frequency
compensation requirements because the output induc-
tor does not contribute to phase delay in the regulator
loop. This current mode technique means that the error
amplifier (nonisolated applications) or the opto-coupler
(isolated applications) commands current (rather than volt-
age) to be delivered to the output. This makes frequency
compensation easier and provides faster loop response
to output load transients.
A resistor divider from the application’s output voltage gen-
erates a voltage at the inverting FB input of the LTC4269-2
error amplifier (or to the input of an external opto-coupler)
and is compared to an accurate reference (1.23V for
LTC4269-2). The error amplifier output (COMP) defines the
input threshold (I
SENSE
) of the current sense comparator.
COMP voltages between 0.8V (active threshold) and 2.5V
define a maximum I
SENSE
threshold from 0mV to 220mV.
By connecting I
SENSE
to a sense resistor in series with the
source of an external power MOSFET, the MOSFET peak
current trip point (turn off) can be controlled by COMP
level and hence by the output voltage. An increase in output
load current causing the output voltage to fall, will cause
COMP to rise, increasing I
SENSE
threshold, increasing the
current delivered to the output. For isolated applications,
the error amplifier COMP output can be disabled to allow
the opto-coupler to take control. Setting FB = V
REF
disables
the error amplifier COMP output, reducing pin current to
(COMP – 0.7)/40k.
Slope Compensation
The current mode architecture requires slope compensation
to be added to the current sensing loop to prevent subhar-
monic oscillations which can occur for duty cycles above
50%. Unlike most current mode converters which have a
slope compensation ramp that is fixed internally, placing a
constraint on inductor value and operating frequency, the
LTC4269-2 has externally adjustable slope compensation.
Slope compensation can be programmed by inserting an
external resistor (R
SLOPE
) in series with the I
SENSE
pin. The
LTC4269-2 has a linear slope compensation ramp which
sources current out of the I
SENSE
pin of approximately 8µA
at 0% duty cycle to 35µA at 80% duty cycle.
Overcurrent Detection and Soft-Start (OC Pin)
An added feature to the LTC4269-2 is a precise 107mV
sense threshold at the OC pin used to detect overcurrent
conditions in the converter and set a soft-start latch. The
OC pin is connected directly to the source of the primary-
side MOSFET to monitor peak current in the MOSFET (Fig-
ure
13). The 107mV threshold is constant over the entire
duty cycle range of the converter because it is unaffected
by the slope compensation added to the I
SENSE
pin.
applicaTions inForMaTion
LTC4269-2
23
42692fb
Synchronizing
A SYNC pin allows the LTC4269-2 oscillator to be synchro-
nized to an external clock. The SYNC pin can be driven
from a logic-level output, requiring less than 0.8V for a
logic-level low and greater than 2.2V for a logic-level high.
Duty cycle should run between 10% and 90%. To avoid
loss of slope compensation during synchronization, the free
running oscillator frequency, f
OSC
, should be programmed
to 80% of the external clock frequency (f
SYNC
). The R
SLOPE
resistor chosen for nonsynchronized operation should be
increased by 1.25x (= f
SYNC
/f
OSC
).
Shutdown and Programming the Power Supply
Undervoltage Lockout
The LTC4269-2 has an accurate 1.32V shutdown threshold
at the SD_V
SEC
pin. This threshold can be used in con-
junction with a resistor divider to define the power supply
undervoltage lockout threshold (UVLO) of the power supply
input voltage (V
S
) (Figure 9). A pin current hysteresis (11µA
before part turn-on, 0µA after part turn-on) allows power
supply UVLO hysteresis to be programmed. Calculation of
the on/off thresholds for the power supply input voltage
can be made as follows:
V
S(OFF)
Threshold = 1.32[1 + (R1/R2)]
V
S(ON)
Threshold = V
S(OFF)
+ (11µA • R1)
Connect the PWRGD pin to the resistive divider network
at the SD_V
SEC
pin to prevent the DC/DC converter from
starting before the PD interface completely charges the
reservoir capacitor, C1 (Figure 9).
The SD_V
SEC
pin must not be left open since there must
be an external source current >11µA to lift the pin past its
1.32V threshold for part turn-on.
Micropower Start-Up: Selection of Start-Up Resistor
and Capacitor for V
IN
The LTC4269-2 uses turn-on voltage hysteresis at the V
IN
pin and low start-up current to allow micropower start-up
(Figure 10). The LTC4269-2 monitors V
IN
pin voltage to
allow the part to turn-on at 14.25V and the part to turn-
off at 8.75V. Low start-up current (460µA) allows a large
resistor to be connected between the power supply input
supply and V
IN
. Once the part is turned on, input current
applicaTions inForMaTion
Figure 9. Programming Power Supply
Undervoltage Lockout (UVLO)
1.32V
POWER SUPPLY
INPUT VOLTAGE (V
S
)
42692 F09
SD_V
SEC
PWRGD
11µA
LTC4269-2
R1
R2
+
–
Figure 10. Low Power Start-Up
1.32V
POWER SUPPLY
INPUT VOLTAGE (V
S
)
FROM AUXILIARY WINDING
*FOR V
S
> 25V, ZENER D1 RECOMMENDED
(V
IN ON(MAX)
< V
Z
< 25V)
42692 F10
V
IN
LTC4269-2
C
START
D1*
R
START
+
–
increases to drive the IC (5.2mA) and the output drivers
(I
DRIVE
). A large enough capacitor is chosen at the V
IN
pin
to prevent V
IN
falling below its turn-off threshold before
a bias winding in the converter takes over supply to V
IN
.
This technique allows a simple resistor/capacitor for
start-up which draws low power from the system supply
to the converter.
For system input voltages exceeding the absolute maximum
rating of the LTC4269-2 V
IN
pin, an external Zener should
be connected from the V
IN
pin to GND. This covers the
condition where V
IN
charges past V
IN(ON)
but the part does
not turn on because SD_V
SEC
< 1.32V. In this condition,
V
IN
will continue to charge towards system V
IN
, possibly
exceeding the rating for the V
IN
pin. The Zener voltage
should obey V
IN(ONMAX)
< V
Z
< 25V.
LTC4269-2
24
42692fb
Programming Oscillator Frequency
The oscillator frequency (f
OSC
) of the LTC4269-2 is pro-
grammed using an external resistor, R
OSC
, connected
between the R
OSC
pin and GND. Figure 11 shows typical
f
OSC
vs R
OSC
resistor values. The LTC4269-2 free-run-
ning oscillator frequency is programmable in the range
of 100kHz to 500kHz.
Stray capacitance and potential noise pickup on the R
OSC
pin should be minimized by placing the R
OSC
resistor as
close as possible to the R
OSC
pin and keeping the area of
the R
OSC
node as small as possible. The ground side of
the R
OSC
resistor should be returned directly to the (analog
ground) GND pin. R
OSC
can be calculated by:
R
OSC
= 9.125k [(4100k/f
OSC
) – 1]
Programming Leading Edge Blank Time
For PWM controllers driving external MOSFETs, noise
can be generated at the source of the MOSFET during
gate rise time and some time thereafter. This noise can
potentially exceed the OC and I
SENSE
pin thresholds of the
LTC4269-2 to cause premature turn-off of SOUT and OUT
pi
ns in addition to false trigger of soft-start. The LTC4269-2
provides a programmable leading edge blanking of the
OC and I
SENSE
comparator outputs to avoid false current
sensing during MOSFET switching.
Blanking is provided in two phases (Figure 12): The first
phase automatically blanks during gate rise time. Gate rise
times can vary depending on MOSFET type. For this reason
the LTC4269-2 performs true ‘leading edge blanking’ by
automatically blanking OC and I
SENSE
comparator outputs
until OUT rises to within 0.5V of V
IN
or reaches its clamp
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to GND. Typical durations for this
portion of the blanking period are from 45ns at R
BLANK
= 10k to 540ns at R
BLANK
= 120k. Blanking duration can
be approximated as:
Blanking (extended) = [45(R
BLANK
/10k)]ns
(See graph in the Typical Performance Characteristics
section).
Programming Current Limit (OC Pin)
The LTC4269-2 uses a precise 107mV sense threshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
duty cycle because it is not affected by slope compensa-
tion programmed at the I
SENSE
pin. The OC pin monitors
the peak current in the primary MOSFET by sensing the
voltage across a sense resistor (R
S
) in the source of the
MOSFET. The overcurrent limit for the converter can be
programmed by:
O
v
ercurrent limit = (107mV/R
S
)(N
P
/N
S
) – (½)(I
RIPPLE
)
applicaTions inForMaTion
Figure 11. Oscillator Frequency, f
OSC
, vs R
OSC
Figure 12. Leading Edge Blank Timing
R
BLANK
(MIN)
= 10k
10k < R
BLANK
b 240k 100ns
(AUTOMATIC)
LEADING
EDGE
BLANKING
(PROGRAMMABLE)
EXTENDED
BLANKING
CURRENT
SENSE
DELAY
OUT
BLANKING
42692 F12
0 Xns
X + 45ns [X + 45(R
BLANK
/10k)]ns
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LTC4269IDKD-2#TRPBF

Mfr. #:
Buy LTC4269IDKD-2#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE802.3at High Power PD Controller with Forward Switcher
Lifecycle:
New from this manufacturer.
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