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The time for SS_MAXDC to fall to a given voltage can be
approximated as:
SS_MAXDC(t
FALL
)=
(C
SS
/I
DIS
) • [SS_MAXDC(DC) – V
SS(MIN)
]
where:
I
DIS
= net discharge current on C
SS
C
SS
= capacitor value at SS_MAXDC pin
SS_MAXDC(DC) = programmed DC voltage
V
SS(MIN)
= minimum SS_MAXDC voltage before
recharge
I
DIS
8e
–4
+ (V
REF
– V
SS(MIN)
)[(1/2R
B
) – (1/R
T
)]
For faults arising from (1) and (2):
V
REF
= 100mV.
For a fault arising from (3):
V
REF
= 2.5V.
SS_MAXDC(DC) = V
REF
[R
B
/(R
T
+ R
B
)]
V
SS(MIN)
= SS_MAXDC reset threshold = 0.45V
(if fault removed before t
FALL
)
Example
For an overcurrent fault (OC > 100mV), V
REF
= 2.5V,
R
T
= 35.7k, R
B
= 100k, C
SS
= 0.1µF and assume
V
SS(MIN)
= 0.45V,
I
DIS
8e
–4
+ (2.5 – 0.45)[(½ • 100k) – (1/35.7k)]
= 8e
–4
+ (2.05)(–0.23e
–4
) = 7.5e
–4
SS_MAXDC(DC) = 1.84V
SS_MAXDC(t
FALL
)
= (1e
–7
/7.5e
–4
) • (1.84 – 0.45)=1.85e
–4
s
If the OC fault is not removed before 185µs then SS_MAXDC
will continue to fall past 0.45V towards a new V
SS(MIN)
.
The typical V
OL
for SS_MAXDC at 150µA is 0.2V.
SS_MAXDC Charge Timing
When all faults are removed and the SS_MAXDC pin
has fallen to its reset threshold of 0.45V or lower, the
SS_MAXDC pin will be released and allowed to charge.
SS_MAXDC will rise until it settles at its programmed DC
voltage—setting the maximum switch duty cycle clamp.
The calculation of charging time for the SS_MAXDC pin
between any two voltage levels can be approximated as
an RC charging waveform using the model shown in
Figure 16.
The ability to predict SS_MAXDC rise time between any two
voltages allows prediction of several key timing periods:
(1)
No
Switching Period (time from SS_MAXDC(DC) to
V
SS(MIN)
+ time from V
SS(MIN)
to V
SS(ACTIVE)
)
(2) Converter Output Rise Time (time from V
SS(ACTIVE
) to
V
SS(REG)
; V
SS(REG)
is the level of SS_MAXDC where
maximum duty cycle clamp equals the natural duty
cycle of the switch)
(3)
T
ime For Maximum Duty Cycle Clamp within X% of
Target Value
The time for SS_MAXDC to charge to a given voltage V
SS
is found by re-arranging:
V
SS
(t) = SS_MAXDC(DC) (1 – e
(–t/RC)
)
to give,
t = RC • (–1) • ln(1 – V
SS
/SS_MAXDC(DC))
where,
V
SS
= SS_MAXDC voltage at time t
SS_MAXDC(DC) = programmed DC voltage setting
maximum duty cycle clamp = V
REF
(R
B
/(R
T
+ R
B
)
R = R
CHARGE
(Figure 16) = R
T
• R
B
/(R
T
+ R
B
)
C = C
SS
(Figure 16)
Example (1) No Switching Period
The period of no switching for the converter, when a soft-
start event has occurred, depends on how far SS_MAXDC
can fall before recharging occurs and how long a fault ex-
ists. It will be assumed that a fault triggering soft-start is
removed before SS_MAXDC can reach its reset threshold
(0.45V).
No Switching Period = t
DISCHARGE
+ t
CHARGE
t
DISCHARGE
= discharge time from SS_MAXDC(DC) to
0.45V
t
CHARGE
= charge time from 0.45V to V
SS(ACTIVE)
t
DISCHARGE
was already calculated earlier as 185µs.
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t
CHARGE
is calculated by assuming the following:
V
REF
= 2.5V, R
T
= 35.7k, R
B
= 100k, C
SS
= 0.1µF and
V
SS(MIN)
= 0.45V.
t
CHARGE
= t(V
SS
= 0.8V) – t(V
SS
= 0.45V)
Step 1:
SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V
R
CHARGE
= (35.7k • 100k/135.7k) = 26.3k
Step 2:
t(V
SS
= 0.45V) is calculated from:
t = R
CHARGE
C
SS
(–1) • ln(1 – V
SS
/SS_MAXDC(DC))
= 2.63e
4
• 1e
–7
• (–1) • ln(1 – 0.45/1.84)
= 2.63e
–3
• (–1) • ln(0.755) = 7.3e
–4
s
Step 3:
t(V
SS
= 0.8V) is calculated from:
t = R
CHARGE
C
SS
(–1) • ln(1 – V
SS
/SS–MAXDC(DC))
= 2.63e
4
• 1e
–7
• (–1) • ln(1 – 0.8/1.84)
= 2.63e
–3
• (–1) • ln(0.565) = 1.5e
–3
s
From Step 1 and Step 2
t
CHARGE
= (1.5 – 0.73)e
–3
s = 7.7e
–4
s
The total time of no switching for the converter due to a
soft-start event
=
t
DISCHARGE
+ t
CHARGE
= 1.85e
–4
+ 7.7e
–4
= 9.55e
–4
s
Example (2) Converter Output Rise Time
The rise time for the converter output to reach regulation
can be closely approximated as the time between the start
of switching (SS_MAXDC = V
SS(ACTIVE)
) and the time where
converter duty cycle is in regulation (DC(REG)) and no
longer controlled by SS_MAXDC (SS_MAXDC = V
SS(REG)
).
Converter output rise time can be expressed as:
Output Rise Time = t(V
SS(REG)
) – t(V
SS(ACTIVE)
)
Step 1: Determine converter duty cycle DC(REG) for output
in regulation.
The natural duty cycle DC(REG) of the converter depends
on several factors. For this example it is assumed that
DC(REG) = 60% for power supply input voltage near the
power supply UVLO. This gives SD_V
SEC
= 1.32V.
Also assume that the maximum duty cycle clamp pro-
grammed for this condition is 72% for SS_MAXDC(DC)
= 1.84V, f
OSC
= 200kHz and R
DELAY
= 40k.
Step 2: Calculate V
SS(REG)
To calculate the level of SS_MAXDC (V
SS(REG)
) that no
longer clamps the natural duty cycle of the converter, the
equation for maximum duty cycle clamp must be used
(see previous section Programming Maximum Duty Cycle
Clamp).
The point where the maximum duty cycle clamp meets
DC(REG) during soft-start is given by:
DC(REG) = Max Duty Cycle Clamp
0.6 = k • 0.522(SS_MAXDC(DC)/SD_V
SEC
) – (t
DELAY
• f
OSC
)
For SD_V
SEC
= 1.32V, f
OSC
= 200kHz and
R
DELAY
= 40k
This gives k = 1 and t
DELAY
= 40ns.
Rearranging the above equation to solve for SS_MAXDC
= V
SS(REG)
= [0.6 + (t
DELAY
• f
OSC
)(SD_V
SEC
)]/(k • 0.522)
= [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522)
= (0.608)(1.32)/0.522 = 1.537V
Step 3: Calculate t(V
SS(REG
)) – t(V
SS(ACTIVE)
)
Recall the time for SS_MAXDC to charge to a given volt-
age V
SS
is given by:
t = R
CHARGE
C
SS
(–1) • ln(1 – V
SS
/SS_MAXDC(DC))
(Figure 16 gives the model for SS_MAXDC charging)
For R
T
= 35.7k, R
B
= 100k, R
CHARGE
= 26.3k
For C
SS
= 0.1µF, this gives t(V
SS(ACTIVE)
)
= t(V
SS(0.8V)
) = 2.63e
4
• 1e
–7
• (–1) • ln(1 – 0.8/1.84)
= 2.63e
–3
• (–1) • ln(0.565) = 1.5e
–3
s
t(V
SS(REG)
) = t(V
SS(1.537V)
) = 26.3k • 0.1µF • –1 •
ln(1 – 1.66/1.84) = 2.63e
–3
• (–1) • ln(0.146) = 5e
–3
s
The rise time for the converter output:
= t(V
SS(REG)
) – t(V
SS(ACTIVE)
) = (5 – 1.5)e
–3
s
= 3.5e
–3
s
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Example (3) Time For Maximum Duty Cycle Clamp to
Reach Within X% of Target Value
A maximum duty cycle clamp of 72% was calculated previ-
ously in the section ‘Programming Maximum Duty Cycle
Clamp’. The programmed value used for SS_MAXDC(DC)
was 1.84V.
The time for SS_MAXDC to charge from its minimum value
V
SS(MIN)
to within X% of SS_MAXDC(DC) is given by:
t(SS_MAXDC charge time within X% of target)
= t[(1 – (X/100) • SS_MAXDC(DC)] – t(V
SS(MIN)
)
For X = 2 and V
SS(MIN)
= 0.45V, t(0.98 • 1.84) – t(0.45)
= t(1.803) – t(0.45)
From previous calculations, t(0.45) = 7.3e
–4
s.
Using previous values for R
T
, R
B
and C
SS
,
t(1.803) = 2.63e
–4
• 1e
–7
• (–1) • ln(1 – 1.803/1.84)
= 2.63e
–3
• (–1) • ln(0.02) = 1.03e
–2
s
Hence the time for SS_MAXDC to charge from its mini-
mum reset threshold of 0.45V to within 2% of its target
value is given by:
t(1.803) – t(0.45) = 1.03e
–2
– 7.3e
–4
= 9.57e
–3
s

LTC4269IDKD-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE802.3at High Power PD Controller with Forward Switcher
Lifecycle:
New from this manufacturer.
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