1. General description
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC573 and 74HCT573.
The 74LV573 consists of eight D-type transparent latches, featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches
are transparent, that is, a latch output will change each time its corresponding D-input
changes. When LE is LOW, the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the latches.
The 74LV573 is functionally identical to the 74LV373, but has a different pin arrangement.
2. Features
n Wide operating voltage: 1.0 V to 5.5 V
n Optimized for low voltage applications: 1.0 V to 3.6 V
n Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
n Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
n Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
n Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
n Useful as input or output port for microprocessors
n Common 3-state output enable input
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Multiple package options
n Specified from −40 °Cto+85°C and from −40 °C to +125 °C
74LV573
Octal D-type transparent latch; 3-state
Rev. 03 — 15 April 2009 Product data sheet
