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74LV573D,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
74LV573_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 4 of 18
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
Fig 5. Pin configuration DIP20, SO20 Fig 6. Pin configuration SSOP20, TSSOP20
74LV573
OE V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND LE
001aaj966
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
74LV573
OE V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND LE
001aaj967
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
OE 1 output enable input (active LOW)
D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output
V
CC
20 supply voltage
Table 3. Functional table
[1]
Operating modes Input Internal latch Output
OE LE Dn Qn
Enable and read register
(transparent mode)
LH L L L
LH H H H
Latch and read register L L l L L
LL h H H
Latch register and disable outputs H L l L Z
HL h H Z
74LV573_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 5 of 18
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of P
tot
derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
[1] The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.5 +7.0 V
I
IK
input clamping current V
I
< −0.5 V or V
I
>V
CC
+ 0.5 V
[1]
-20mA
I
OK
output clamping current V
O
< −0.5 V or V
O
>V
CC
+ 0.5 V
[1]
-50mA
I
O
output current V
O
= −0.5 V to (V
CC
+ 0.5 V) - 35 mA
I
CC
supply current - 70 mA
I
GND
ground current −70 - mA
T
stg
storage temperature −65 +150 °C
P
tot
total power dissipation T
amb
= −40 °C to +125 °C
[2]
DIP20 - 750 mW
SO20, SSOP20 and TSSOP20 - 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage
[1]
1.0 3.3 5.5 V
V
I
input voltage 0 - V
CC
V
V
O
output voltage 0 - V
CC
V
T
amb
ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate V
CC
= 1.0 V to 2.0 V - - 500 ns/V
V
CC
= 2.0 V to 2.7 V - - 200 ns/V
V
CC
= 2.7 V to 3.6 V - - 100 ns/V
V
CC
= 3.6 V to 5.5 V - - 50 ns/V
74LV573_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 6 of 18
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
9. Static characteristics
[1] Typical values are measured at T
amb
= 25 °C.
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
V
IH
HIGH-level input voltage V
CC
= 1.2 V 0.9 - - 0.9 - V
V
CC
= 2.0 V 1.4 - - 1.4 - V
V
CC
= 2.7 V to 3.6 V 2.0 - - 2.0 - V
V
CC
= 4.5 V to 5.5 V 0.7V
CC
- - 0.7V
CC
-V
V
IL
LOW-level input voltage V
CC
= 1.2 V - - 0.3 - 0.3 V
V
CC
= 2.0 V - - 0.6 - 0.6 V
V
CC
= 2.7 V to 3.6 V - - 0.8 - 0.8 V
V
CC
= 4.5 V to 5.5 V - - 0.3V
CC
- 0.3V
CC
V
V
OH
HIGH-level output voltage V
I
= V
IH
or V
IL
I
O
= −100 µA; V
CC
= 1.2 V - 1.2 - - - V
I
O
= −100 µA; V
CC
= 2.0 V 1.8 2.0 - 1.8 - V
I
O
= −100 µA; V
CC
= 2.7 V 2.5 2.7 - 2.5 - V
I
O
= −100 µA; V
CC
= 3.0 V 2.8 3.0 - 2.8 - V
I
O
= −100 µA; V
CC
= 4.5 V 4.3 4.5 - 4.3 - V
I
O
= −8 mA; V
CC
= 3.0 V 2.4 2.82 - 2.2 - V
I
O
= −16 mA; V
CC
= 4.5 V 3.6 4.2 - 3.5 - V
V
OL
LOW-level output voltage V
I
= V
IH
or V
IL
I
O
= 100 µA; V
CC
= 1.2 V - 0 - - - V
I
O
= 100 µA; V
CC
= 2.0 V - 0 0.2 - 0.2 V
I
O
= 100 µA; V
CC
= 2.7 V - 0 0.2 - 0.2 V
I
O
= 100 µA; V
CC
= 3.0 V - 0 0.2 - 0.2 V
I
O
= 100 µA; V
CC
= 4.5 V - 0 0.2 - 0.2 V
I
O
= 8 mA; V
CC
= 3.0 V - 0.20 0.40 - 0.50 V
I
O
= 16 mA; V
CC
= 4.5 V - 0.35 0.55 - 0.65 V
I
I
input leakage current V
I
=V
CC
or GND;
V
CC
= 5.5 V
- - 1.0 - 1.0 µA
I
OZ
OFF-state output current V
I
=V
IH
or V
IL
;
V
O
=V
CC
or GND;
V
CC
= 5.5 V
--5 - 10µA
I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
- - 20 - 160 µA
∆I
CC
additional supply current per input; V
I
= V
CC
− 0.6 V;
V
CC
= 2.7 V to 3.6 V
- - 500 - 850 µA
C
I
input capacitance - 3.5 - - - pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

74LV573D,112

Mfr. #:
Buy 74LV573D,112
Manufacturer:
NXP Semiconductors
Description:
Latches OCTAL TRANSPARANT LATCH
Lifecycle:
New from this manufacturer.
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