10©2016 Integrated Device Technology, Inc Revision A March 4, 2016
83PN156I Data Sheet
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50
applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50
. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
VCC
XTAL_OUT
XTAL_IN
R1
100
R2
100
Zo = 50 ohmsRs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTA L_ OU T
XTA L_ I N
Zo = 50 ohms
C2
.1uf
LVPECL Driver
Zo = 50 ohms
R1
50
R2
50
R3
50
11©2016 Integrated Device Technology, Inc Revision A March 4, 2016
83PN156I Data Sheet
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be used
for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
12©2016 Integrated Device Technology, Inc Revision A March 4, 2016
83PN156I Data Sheet
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to V
CC
– 2V. For V
CC
= 2.5V, the V
CC
– 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5C. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250
Ω
R3
250
Ω
R2
62.5
Ω
R4
62.5
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
R3
18
Ω
+

83PN156DKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner OSCILLATOR REPLACEMENT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet