9©2016 Integrated Device Technology, Inc Revision A March 4, 2016
83PN156I Data Sheet
Applications Information
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 1. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally
/Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Crystal Input Interface
The 83PN156I has been characterized with 12pF parallel resonant
crystals. The capacitor values shown in Figure 2A below were
determined using a 25MHz, 12pF parallel resonant crystal and were
chosen to minimize the ppm error. Other parallel resonant crystal’s
values can be used. For example, a crystal with a C
L
= 18pF can be
used, but would require the tuning capacitors to be adjusted.
Figure 2A. Crystal Input Interface, using 12pF crystal
Figure 2B. Crystal Input Interface, using 18pF crystal
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
XTAL_IN
XTAL_OUT
X1
12pF Parallel Crystal
C1
4pF
C2
4pF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
16pF
C2
16pF
