NTB5405N, NVB5405N
http://onsemi.com
4
TYPICAL PERFORMANCE CURVES
Figure 7. Capacitance Variation
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
5
0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
25
Figure 10. Diode Forward Voltage vs. Current
0.80.6
20
15
R
G
, GATE RESISTANCE (OHMS)
1 10 100
10
1
t, TIME (ns)
V
DS
= 32 V
I
D
= 40 A
V
GS
= 10 V
t
r
t
d(on)
1000
t
f
t
d(off)
10
40
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
0
6
0
Q
G
, TOTAL GATE CHARGE (nC)
8
20 40 60
I
D
= 40 A
T
J
= 25°C
V
GS
Q
GS
90
Q
GD
QT
4
2
7050
0.4 0.70.5
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
18
0
24
12
6
V
DS
V
DS
= 0 V V
GS
= 0 V
201010
4000
2000
0
40
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
T
J
= 25°C
C
oss
C
iss
C
rss
0
6000
V
GS
V
DS
30
C
rss
C
iss
80
100
0.9 1
3000
1000
7000
5000
10 30
35
30
10 30
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0
200
400
600
800
25 50 75 100 125 150 17
T
J
, STARTING JUNCTION TEMPERATURE (°C)
AVALANCHE ENERGY (mJ)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
I
D
= 40 A
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
D
0.1
10
100
1000
0.1 10 100
10 s
100 s
1 ms
10 ms
dc
V
GS
= 20 V
Single Pulse
T
C
= 25°C
R
DS(on)
Limit
Thermal Limit
Package Limit
1
1
100
300
500
700
