LTC3226
9
3226fa
OPERATION
The LTC3226 is a 2-cell series supercapacitor charger
designed to back up a Li-ion battery or any system rail
in the range of 2.5V to 5.3V. It has four principal circuit
components: a dual mode (1x/2x) charge pump with an
integrated balancer and a voltage clamp, an LDO to supply
the load current from the charge stored on the superca-
pacitor, an ideal diode controller to control the gate of the
external FET between V
IN
and V
OUT
, and a PFI comparator
to decide whether to activate the charge pump to charge the
supercapacitor stack or to activate the LDO to supply the
load when V
IN
falls below an externally programmed value.
The LTC3226 has two modes of operation: normal and
backup. If V
IN
is above an externally programmable PFI
threshold voltage, the part is in normal mode in which
power flows from V
IN
to V
OUT
through the external FET
and the internal charge pump stays on to top off the
supercapacitor stack. If V
IN
is below this PFI threshold,
the part is in backup mode. In this mode, the internal
charge pump is turned off, the external FET is turned off
and the LDO is turned on to supply the load current from
the stored charge.
CHARGE PUMP
One of the principal circuit components of the LTC3226
is a dual mode low noise constant frequency (0.9MHz)
regulated charge pump which transfers charge from V
IN
and stores it onto the supercapacitor stack at the CPO pin.
The target or termination voltage on the CPO pin is pro-
grammed by an external resistor divider using the CPO_FB
pin. The input current limit to the charger is programmed
by an external resistor between the PROG pin and ground.
The charge pump turns on when V
IN
exceeds the externally
programmable PFI threshold. At the beginning of the charge
cycle when the CPO pin voltage is less than V
IN
, the charge
pump is in 1x mode (linear mode) in which the charge pump
acts as a pass element and charges the supercapacitor with
a charge current that is limited by the programmed input
current limit. As the CPO voltage rises to within 200mV of
the input supply voltage, the charge pump switches to 2x
mode (doubler mode) in which the average charge current
is approximately equal to half the input current limit. As the
CPO voltage exceeds the target value by approximately 1%,
the charge pump switches turn off and the charge pump
enters the sleep mode. In sleep mode, most of the charge
pump control circuitry is turned off to minimize quiescent
current. As the supercapacitor discharges due to leakage
and internal quiescent current load, the CPO pin voltage
slowly drops. When the CPO pin voltage drops 1% below
the programmed voltage, the charge pump turns on to
replenish charge on the supercapacitor and the cycle con-
tinues. The charge pump can be turned off by pulling the
EN_CHG pin below 0.4V. However, by default, the charge
pump is always enabled via an internal low current pull-up
circuit if the EN_CHG pin is left floating.
Voltage Clamp
The LTC3226 charge pump is equipped with circuitry to
limit the voltage across any supercapacitor in the stack
to a maximum allowable preset voltage of 2.65V. If the
voltage across the top capacitor (VMID-V
CPO
) ever gets
to 2.65V before the CPO pin reaches the target voltage,
the charge pump stops charging the top of the stack via
the CPO pin, switches to 1x mode and delivers charge
directly to the bottom capacitor via the VMID pin until the
stack voltage reaches its programmed value. If the voltage
across the bottom capacitor reaches 2.65V before the
stack gets to its target value, the charge pump continues
to deliver charge to the top of the stack via the CPO pin
and a shunt regulator turns on to bleed charge off of the
bottom capacitor and prevents the VMID pin voltage from
rising any further. The shunt regulator is able to shunt the
maximum allowable charge current which is approximately
315mA (in 1x mode). In the event both capacitors exceed
2.65V, the charge pump enters sleep mode by turning off
most of its circuitry.
Leakage Balancer
The LTC3226 is equipped with an internal leakage balanc-
ing amplifier which servos the VMID pin voltage to exactly
half of the CPO pin voltage. However, it has limited source
(~4.5mA) and sink (~5.5mA) capability. It is designed to
handle slight mismatch of the supercapacitors due to
leakage currents; not to correct any gross mismatch due
to defects. The balancer is only active as long as the input
supply voltage is above the PFI threshold. The internal bal-
ancer eliminates the need for external balancing resistors.
