Low Voltage DC Motor Driver
A3918
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Device Operation The A3918 is a full-bridge low voltage
motor driver capable of operating one high current DC motor.
MOSFET output stages substantially reduce the voltage drop and
the power dissipation of the outputs of the A3918, compared to
typical drivers with bipolar transistors.
Output current can be regulated by pulse width modulating
(PWM) the inputs. In addition supporting external PWM of the
driver, the A3918 limits the peak current by internally PWMing
the source driver when the current in the winding exceeds the
peak current, which is determined by a sense resistor. A fault
output notifies the user that peak current was reached. If internal
current limiting is not needed, the sense pin should be shorted to
ground.
Internal circuit protection includes thermal shutdown with hyster-
esis, undervoltage lockout, internal clamp diodes, and crossover
current protection.
The A3918 is designed for portable applications, providing a
power-off low current sleep mode and an operating voltage of
2.5 to 9 V.
External PWM Output current regulation can be achieved by
pulse width modulating the inputs. Slow decay mode is selected
by holding one input high while PWMing the other input. Hold-
ing one input low and PWMing the other input results in fast
decay. Refer to the Applications Information section for further
information.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched. The comparator
output is blanked to prevent false overcurrent detections due to
reverse recovery currents of the clamp diodes or to switching
transients related to the capacitance of the load. The blank time,
t
BLANK
, is approximately 3 μs.
Sleep Mode An active-low control input used to minimize
power consumption when the A3918 is not in use. This dis-
ables much of the internal circuitry including the output drivers,
internal regulator, and charge pump. A logic high allows normal
operation. When coming out of sleep mode, wait 1.5 ms before
issuing a command, to allow the internal regulator and charge
pump to stabilize.
Enable When all logic inputs are pulled to logic low, the outputs
of the bridges are disabled. The charge pump and internal cir-
cuitry continue to run when the outputs are disabled.
Charge Pump (CP1, CP2, CP3, and CP4) When supply volt-
ages are lower than 3.5 V, the two-stage charge pump triples the
input voltage to a maximum of 7 V above the supply. The charge
pump is used to create a supply voltage greater than V
BB
, to drive
the source-side DMOS gates. For pumping purposes, a 0.1 μF
ceramic capacitor should be connected between CP1 and CP2,
and between CP3 and CP4. A 0.1 uF ceramic capacitor is required
between VCP and VBB, to act as a reservoir to operate the high-
side DMOS devices.
Thermal Shutdown The A3918 will disable the outputs if the
junction temperature reaches 165°C. When the junction tempera-
ture drops 15°C, the outputs will be enabled.
Brake Mode When driving DC motors, the A3918 goes into
brake mode (turns on both sink drivers) when both of its inputs
are high (IN1 and IN2). There is no protection during braking, so
care must be taken to ensure that the peak current during braking
does not exceed the absolute maximum current.
Internal PWM Current Control The bridge is controlled
by a fixed off-time PWM current control circuit that limits the
load current to a desired value, I
TRIP
. Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and the current sense resistor, R
SENSE
.
When the voltage across R
SENSE
equals the internal reference
voltage, the current sense comparator resets the PWM latch,
which turns off the source driver.
The maximum value of current limiting, I
TRIP
(max) , is set by the
selection of the sense resistor, R
SENSE
, and is approximated by a
transconductance function:
I
TRIP
(max) = 0.2 / R
SENSE
.
It is critical to ensure the maximum rating on the SENSE pin
(0.5 V) is not exceeded.
Synchronous Rectification When a PWM off-cycle is trig-
gered by an internal fixed off-time cycle, load current recirculates
in slow decay SR mode. During slow decay, current recirculates
through the sink-side FET and the sink-side body diode. The SR
feature enables the sink-side FET, effectively shorting out the
body diode. The sink driver is not enabled until the source driver
is turned off and the crossover delay has expired. This feature
helps lower the voltage drop during current recirculation, lower-
ing power dissipation in the bridge.
Overcurrent Output Flag When the peak current (set by the
external resistor) is reached, the fault pin, FL, is pulled low.
When a reset of the PWM latch occurs, the fault timer begins. At
each PWM latch reset, the timer is reset to zero. After approxi-
mately 300 μs, if no peak current event was triggered, the timer
expires and the fault is released. This ensures that during PWM
current limiting, the fault pin remains in a fault state.
