Data Sheet AD5301/AD5311/AD5321
Rev. C | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A0
PD
V
OUT
GND
V
DD
SCL
SDA
A1
AD5301/
AD5311/
AD5321
00927-004
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
GND
SDA
SCL
V
DD
A0
V
OUT
AD5301/
AD5311/
AD5321
0
0927-003
1
2
3
6
5
4
TOP VIEW
(Not to Scale)
Figure 3. 8-Lead MSOP (RM-8) Pin Configuration Figure 4. 6-Lead SOT-23 (RJ-6) Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
MSOP SOT-23
1 6 V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be
decoupled with a 10 μF in parallel with a 0.1 μF capacitor to GND.
2 5 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
3 Not applicable A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
4 4 V
OUT
Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
5 Not applicable
PD
Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software
power-down option. The DAC output goes three-state and the current consumption of the part
drops to 50 nA at 3 V (200 nA at 5 V).
6 3 SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input
shift register. Clock rates of up to 400 kbps can be accommodated in the I
2
C-compatible interface.
SCL may be CMOS/TTL driven.
7 2 SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input
shift register during the write cycle and to read back one or two bytes of data (one byte for the
AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain
data line that should be pulled to the supply with an external pull-up resistor. If not used in
readback mode, SDA may be CMOS/TTL driven.
8 1 GND Ground Reference Point for All Circuitry on the Device.
AD5301/AD5311/AD5321 Data Sheet
Rev. C | Page 8 of 24
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL vs. code plots can be seen in Figure 5 to
Figure 7.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonic-
ity. These DACs are guaranteed monotonic by design over all
codes. Typical DNL vs. code plots can be seen in Figure 8 to
Figure 10.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x00) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error of the AD5301/AD5311/
AD5321 is always positive because the output of the DAC
cannot go below 0 V, due to a combination of the offset errors
in the DAC and output amplifier. It is expressed in millivolts
(see Figure 12).
Full-Scale Error (FSR)
Full-scale error is a measure of the output error when full
scale is loaded to the DAC register. Ideally, the output should
be V
DD
– 1 LSB. Full-scale error is expressed in percent of FSR.
A plot can be seen in Figure 12.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Major Code Transition Glitch Energy
Major code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB
at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00
to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s and vice versa.
Data Sheet AD5301/AD5311/AD5321
Rev. C | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.5
0
–0.5
–1.0
0 50 100 150 200 255
INL ERROR (LSB)
CODE
T
A
= 25°C
V
DD
= 5V
0
0927-005
Figure 5. AD5301 Typical INL Plot
3
1
0
–2
–3
0 200 400 600 800 1023
INL ERROR (LSB)
CODE
T
A
= 25°C
V
DD
= 5V
–1
2
00927-006
Figure 6. AD5311 Typical INL Plot
3
1
0
–8
–12
0 1000 2000 3000 4095
INL ERROR (LSB)
CODE
–4
2
T
A
= 25°C
V
DD
= 5V
00927-007
Figure 7. AD5321 Typical INL Plot
0.3
0.1
0
–0.2
–0.3
0 50 100 150 255
DNL ERROR (LSB)
CODE
–0.1
0.2
200
T
A
= 25°C
V
DD
= 5V
00927-008
Figure 8. AD5301 Typical DNL Plot
0.6
0.2
0
–0.4
–0.6
0 200 400 600 800 1023
DNL ERROR (LSB)
CODE
–0.2
0.4
T
A
= 25°C
V
DD
= 5V
00927-009
Figure 9. AD5311 Typical DNL Plot
1.0
0.5
0
–0.5
–1.0
0 1000 2000 3000 4095
DNL ERROR (LSB)
CODE
T
A
= 25°C
V
DD
= 5V
00927-010
Figure 10. AD5321 Typical DNL Plot

AD5301BRTZ-500RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC I2C 8-BIT Vout
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New from this manufacturer.
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