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AD5311BRMZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
2.5 V to 5.5 V, 120 μA, 2-Wire Interface,
Voltage-Output 8-/10-/12-Bit DACs
Data Sheet
AD5301/AD5311/AD5321
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
AD5301: buffered voltage output 8-bit DAC
AD5311: buffered voltage output 10-bit DAC
AD5321: buffered voltage output 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 120 μA at 3 V
2-wire (I
2
C-compatible) serial interface
Data readback capability
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 50 nA at 3 V
Reference derived from power supply
Power-on reset to 0 V
On-chip rail-to-rail output buffer amplifier
3 power-down functions
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321
1
are single 8-/10-/12-bit, buff-
ered, voltage-output DACs that operate from a single 2.5 V to
5.5 V supply, consuming 120 μA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/μs. It uses a 2-wire (I
2
C-compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can share
the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
devices incorporate a power-on reset circuit, which ensures that
the DAC output powers up to 0 V and remains there until a
valid write takes place. The devices contain a power-down
feature that reduces the current consumption of the device to
50 nA at 3 V and provides software-selectable output loads
while in power-down mode.
The low power consumption in normal operation makes these
DACs ideally suited to portable battery-operated equipment. The
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 μW in all power-down modes.
FUNCTIONAL BLOCK DIAGRAM
RESISTOR
NETWORK
BUFFER
DAC
REGISTER
POWER-DOWN
LOGIC
AD5301/AD5311/AD5321
V
DD
SCL
A0
GND
A1*
REF
POWER-ON
RESET
PD*
SDA
*AVAILABLE ON 8-LEAD VERSION ONLY
INTERFACE
LOGIC
8-/10-/12-BIT
DAC
V
OUT
00927-001
Figure 1.
1
Protected by U.S. Patent No. 5684481.
AD5301/AD5311/AD5321 Data Sheet
Rev. C | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 13
Digital-to-Analog ....................................................................... 13
Resistor String ............................................................................. 13
Output Amplifier ........................................................................ 13
Power-On Reset .......................................................................... 13
Serial Interface ................................................................................ 14
2-Wire Serial Bus ........................................................................ 14
Input Shift Register .................................................................... 14
Write Operation.......................................................................... 15
Read Operation........................................................................... 16
Power-Down Modes .................................................................. 17
Applications Notes ......................................................................... 18
Using the REF193/REF195 as a Power Supply ........................ 18
Bipolar Operation Using the AD5301/ AD5311/AD5321 .... 18
Multiple Devices on One Bus ................................................... 18
CMOS Driven SCL and SDA Lines.......................................... 18
Power Supply Decoupling ......................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016—Rev. B to Rev. C
Changes to Figure 33 and Figure 34 ............................................. 16
Changes to Ordering Guide .......................................................... 22
3/2007—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 4 ............................................................................ 6
Changes to Figure 4 Caption ........................................................... 7
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
11/2003—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions ....................................................... 15
7/1999—Revision 0: Initial Version
Data Sheet AD5301/AD5311/AD5321
Rev. C | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
B Version
1
Parameter
2
Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE
3, 4
AD5301
Resolution 8 Bits
Relative Accuracy
±0.15
LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes.
AD5311
Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes.
AD5321
Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB
Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed monotonic by design over all codes.
Zero-Code Error 5 20 mV All zeros loaded to DAC, see Figure 12.
Full-Scale Error ±0.15 ±1.25 % of FSR All ones loaded to DAC, see Figure 12.
Gain Error ±0.15 ±1 % of FSR
Zero-Code Error Drift
5
–20 μV/°C
Gain Error Drift
5
−5
ppm of
FSR/°C
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage 0.001 V
This is a measure of the minimum drive capability of the
output amplifier.
Maximum Output Voltage V
DD
− 0.001 V
This is a measure of the maximum drive capability of the
output amplifier.
DC Output Impedance
1
Ω
Short-Circuit Current 50 mA V
DD
= 5 V.
20 mA V
DD
= 3 V.
Power-Up Time 2.5 μs Coming out of power-down mode. V
DD
= 5 V.
6 μs Coming out of power-down mode. V
DD
= 3 V.
LOGIC INPUTS (A0, A1, PD)
5
Input Current ±1 μA
Input Low Voltage, V
IL
V
V
DD
= 5 V ± 10%.
0.6 V V
DD
= 3 V ± 10%.
0.5 V V
DD
= 2.5 V.
Input High Voltage, V
IH
2.4 V V
DD
= 5 V ± 10%.
2.1 V V
DD
= 3 V ± 10%.
2.0 V V
DD
= 2.5 V.
Pin Capacitance 3 pF
LOGIC INPUTS (SCL, SDA)
5
Input High Voltage, V
IH
0.7 × V
DD
V
DD
+ 0.3 V
Input Low Voltage, V
IL
−0.3 +0.3 × V
DD
V
Input Leakage Current, I
IN
μA
V
IN
= 0 V to V
DD
.
Input Hysteresis, V
HYST
0.05 × V
DD
V
Input Capacitance, C
IN
6 pF
Glitch Rejection
6
50 ns Pulse width of spike suppressed.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD5311BRMZ-REEL7

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Digital to Analog Converters - DAC 12C 10-BIT VOUT IC 7uS
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