Data Sheet AD5301/AD5311/AD5321
Rev. C | Page 5 of 24
AC CHARACTERISTICS
1
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
B Version
2
Parameter
3
Min Typ Max Unit Test Conditions/Comments
Output Voltage Settling Time V
DD
= 5 V
AD5301 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5311 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5321 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate 0.7 V/μs
Major-Code Change Glitch Impulse 12 nV-s 1 LSB change around major carry
Digital Feedthrough 0.3 nV-s
1
See the Terminology section.
2
Temperature range for the B Version is as follows: –40°C to +105°C.
3
Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
1
V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
2
Limit at T
MIN
,
T
MAX,
B Version Unit Test Conditions/Comments
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 μs min SCL cycle time
t
2
0.6 μs min t
HIGH
, SCL high time
t
3
1.3 μs min t
LOW
, SCL low time
t
4
0.6 μs min t
HD,STA
, start/repeated start condition hold time
t
5
100 ns min t
SU,DAT,
data setup time
t
6
3
0.9 μs max t
HD,DAT
, data hold time
0 μs min
t
7
0.6 μs min t
SU,STA
, setup time for repeated start
t
8
0.6 μs min t
SU,STO
, stop condition setup time
t
9
1.3 μs min t
BUF
, bus free time between a stop condition and a start condition
t
10
300 ns max t
R
, rise time of both SCL and SDA when receiving
4
0 ns min May be CMOS driven
t
11
250 ns max t
F
, fall time of SDA when receiving
4
300 ns max t
F
, fall time of both SCL and SDA when transmitting
4
20 + 0.1C
b
5
ns min
C
b
400 pF max Capacitive load for each bus line
1
See Figure 2.
2
Guaranteed by design and characterization, not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the V
IH MIN
of the SCL signal) in order to bridge the undefined region of the
falling edge of the SCL.
4
t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
5
C
b
is the total capacitance of one bus line in picofarads.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
SDA
SCL
t
9
t
3
t
10
t
4
t
6
t
5
t
2
t
11
t
7
t
4
t
1
t
8
00927-002
Figure 2. 2-Wire Serial Interface Timing Diagram
