MAX8620Y
LDO Output-Voltage
Selection (SEL1, SEL2)
As shown in Table 1, the LDO output voltages, OUT1
and OUT2, are set according to the logic states of
SEL1 and SEL2. SEL1 and SEL2 are trilevel inputs: IN1,
open, and GND. The input voltage, V
IN1
, must be a
dropout voltage (V
DO
) greater than the selected OUT1
and OUT2 voltages.
Power-Enable Input (PWR_ON)
Drive PWR_ON low to place the MAX8620Y in power-
down mode and reduce supply current to 5.5µA (typ).
Connect PWR_ON to IN1 = IN2 or logic-high to enable
the MAX8620Y. EN2 enables and disables OUT2 when
PWR_ON is high (Table 2). OUT1, OUT2, and OUT3 are
all disabled when PWR_ON is low. HF_PWR can tem-
porarily bring the MAX8620 out of power-down mode
when PWR_ON is low (see the HF_PWR section). In
power-down, the control circuitry, internal-switching p-
channel MOSFET, and the internal synchronous rectifier
(n-channel MOSFET) turn off, and LX becomes high
impedance. In addition, both LDOs are disabled.
OUT2 Enable (
EN2
)
Drive EN2 low to enable OUT2. Drive EN2 high to dis-
able OUT2. If the MAX8620Y is placed into power-
down using PWR_ON (PWR_ON = low), OUT2 does not
power regardless of the status of EN2 (Table 2).
µPMIC for Microprocessors or DSPs
in Portable Equipment
10 ______________________________________________________________________________________
ON/OFF
LOGIC
1.25V
REF
87%
REGULATION
P
OUT1
RESET
GND
IN1
LDO THERMAL
SENSOR
MOS DRIVER
WITH I
LIMIT
MOS DRIVER
WITH I
LIMIT
POK
EN2
ERROR-
AMP 2
ERROR-
AMP 1
P
OUT2
PWR_ON
HF_PWR
BP
TIMER
MAX8620Y
Figure 3. Linear-Regulator Functional Diagram
Hands-Free Enable Input (HF_PWR)
A rising edge at HF_PWR generates an internal one-
shot pulse that enables the MAX8620Y for 1.31s (t
HF
). If
HF_PWR remains high after t
HF
expires, the MAX8620Y
reenters shutdown. During t
HF
,
OUT3 and OUT1 are
enabled so the microprocessor (µP) can initialize and
assert a logic-high at PWR_ON. OUT2 enables during
t
HF
if EN2 is low. Once PWR_ON is high, the status of
HF_PWR is ignored. If PWR_ON remains low after t
HF
expires, the MAX8620Y reenters shutdown.
Power-Supply Sequencing
The step-down converter output (OUT3) always powers
up first and powers down last (Figure 4). OUT1 powers
approximately 70µs after OUT3, and OUT2 powers
approximately 50µs after V
OUT1
reaches 87% (typ) of
its regulation voltage. When PWR_ON goes low, OUT1
turns off, then OUT2 turns off, then OUT3 turns off 50µs
after PWR_ON goes low.
MAX8620Y
µPMIC for Microprocessors or DSPs
in Portable Equipment
______________________________________________________________________________________ 11
HF_PWR
PWR_ON
OUT3
OUT1
t
SU2
V
THR
t
SU1
t
RP
t
HF
OUT2
RESET
EN2
50µs
Figure 4. MAX8620Y Power-Supply Sequencing
Table 2. MAX8620Y Power Modes
PWR_ON HF_PWR* EN2 OUT1 AND OUT3 OUT2
1 X 1 Enabled Disabled
1 X 0 Enabled Enabled
0 1 1 Enabled Disabled
0 1 0 Enabled Enabled
0 0 X Disabled Disabled
*A rising edge at HF_PWR initiates a 1.31s one-shot timer. The status of HF_PWR shown in Table 2 indicates whether the one-shot
period has expired as follows:
1 = During t
HP
0 = t
HP
has expired
MAX8620Y
Reset Output (
RESET
)
RESET is an open-drain, active-low output that indi-
cates the status of OUT1. RESET is typically pulled up
through a 100k resistor to the system logic voltage.
RESET asserts at power-up. The reset timer begins
once V
OUT1
reaches 87% of regulation. RESET
deasserts 60ms after V
OUT1
rises above 87% (typ) of
regulation (see the Typical Operating Characteristics).
RESET also asserts when OUT1 is disabled.
Reference Bypass Capacitor Node (BP)
An optional 0.01µF bypass capacitor at BP creates a
lowpass filter for LDO noise reduction. OUT1 and OUT2
exhibit 45µV
RMS
of output-voltage noise with C
BP
=
0.01µF and C
OUT1
= C
OUT2
= 4.7µF.
Undervoltage Lockout
V
IN1
= V
IN
2
must exceed the 2.85V typical undervolt-
age-lockout threshold (V
UVLO
) before the MAX8620Y
enables OUT3 to begin power-supply sequencing (see
the Power-Supply Sequencing section). The UVLO
threshold hysteresis is typically 0.5V.
Current Limiting
The MAX8620Y 300mA LDOs limit their output current to
I
LIM_
= 550mA (typ). If the LDO output current exceeds
I
LIM_
, the corresponding LDO output voltage drops. The
step-down converter limits I
LIM3P
to 675mA (min).
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX8620Y. Independent thermal-protection
circuits monitor the step-down converter and the linear-
regulator circuits. When the MAX8620Y junction temper-
ature exceeds T
J
= +160°C, the thermal-overload
protection circuit disables the corresponding circuitry,
allowing the IC to cool. The thermal-overload protection
circuitry enables the MAX8620Y after the junction tem-
perature cools by 15°C, resulting in a pulsed output dur-
ing continuous thermal-overload conditions. Thermal-
overload protection safeguards the MAX8620Y in the
event of fault conditions. For continuous operation, do
not exceed the absolute-maximum junction-tempera-
ture rating of T
J
= +150°C.
Applications Information
Power-On Closed-Loop System
When the MAX8620Y is used in conjunction with a
microcontroller, HF_PWR and PWR_ON can implement
a short-key power-on closed-loop system (Figure 5).
The MAX8620Y detects a rising edge at HF_PWR and
generates an internal 1.31s (typ) one-shot pulse that
begins power sequencing and temporarily enables
OUT1, OUT2, and OUT3 (depending on the state of
EN2). The 1.31s of power provides time for the proces-
sor to initialize and assert a logic-high at PWR_ON.
Once PWR_ON is driven high, OUT3, OUT1, and OUT2
(depending on the state of EN2) remain enabled. If the
microcontroller does not drive PWR_ON high during
t
HF
, the MAX8620Y disables OUT1, OUT2, and OUT3,
and reenters shutdown.
µPMIC for Microprocessors or DSPs
in Portable Equipment
12 ______________________________________________________________________________________
PWR_ON
µP
POWER-ON
KEY
POWER-HOLD SIGNAL
HF_PWR
V
CORE
V
I/O
V
ANA
1M
PWR HOLD
MAX8620Y
Figure 5. Short-Key Power-On Closed-Loop System

MAX8620YETD+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Power Management Specialized - PMIC uPMIC for MPU/DSP in Portable Equipment
Lifecycle:
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