MAX8620Y
µPMIC for Microprocessors or DSPs
in Portable Equipment
______________________________________________________________________________________ 15
Capacitor Selection
Step-Down Converter Output Capacitor
The output capacitor, C
OUT3
, is required to keep the
output voltage ripple small and to ensure regulation
loop stability. C
OUT3
must have low impedance at the
switching frequency. Ceramic capacitors with X5R or
X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
Due to the unique feedback network, the output capac-
itance can be very low. For most applications, a 2.2µF
capacitor is sufficient. For optimum load-transient per-
formance and very low output ripple, the output capaci-
tor value in µFs should be equal to or larger than the
inductor value in µHs.
Input Capacitor
The input capacitor, C
IN
, reduces the current peaks
drawn from the battery or input power source and
reduces switching noise in the IC. The impedance of
C
IN
at the switching frequency should be kept very low.
Ceramic capacitors with X5R or X7R dielectrics are
highly recommended due to their small size, low ESR,
and small temperature coefficients. Use a 10µF ceram-
ic capacitor or equivalent amount of multiple capacitors
in parallel between IN1 and GND. Connect C
IN
as
close as possible to the MAX8620Y to minimize the
impact of PC board trace inductance.
Feed-Forward Capacitor
The feed-forward capacitor, C
FF
, sets the feedback
loop response, controls the switching frequency, and is
critical in obtaining the best efficiency possible.
Choose a small ceramic C0G (NPO) or X7R capacitor
with a value given by:
where R1 is the resistor between LX and FB (Figure 2).
Select the closest standard value to C
FF
as possible.
LDO Output Capacitors
For applications that require greater than 150mA of out-
put current, connect a 4.7µF ceramic capacitor
between the LDO output and GND. For applications
that require less than 150mA of output current, connect
a 2.2µF ceramic capacitor between the LDO output
and GND. The LDO output capacitor’s (C
OUT_
) equiva-
lent series resistance (ESR) affects stability and output
noise. Use output capacitors with an ESR of 0.1Ω or
less to ensure stability and optimum transient response.
Surface-mount ceramic capacitors have very low ESR
and are commonly available in values up to 10µF.
Connect C
OUT
as close as possible to the MAX8620Y
to minimize the impact of PC board trace inductance.
Power Dissipation and Thermal
Considerations
The MAX8620Y total power dissipation, P
D
, is estimat-
ed using the following equations:
`
where P
IN(OUT3)
is the input power for OUT3, η is the
step-down converter efficiency, and R
DC(INDUCTOR)
is
the inductor’s DC resistance.
The die junction temperature can be calculated as follows:
where θ
JA
= 55°C/W at +70°C.
T
J
should not exceed +150°C in normal operating con-
ditions.
PC Board Layout and Routing
High switching frequencies and relatively large peak
currents make the PC board layout a very important
aspect of design. Good design minimizes excessive
EMI on the feedback paths and voltage gradients in the
ground plane, both of which can result in instability or
regulation errors. Connect C
IN
close to IN1 and GND.
Connect the inductor and output capacitors (C
OUT3
) as
close to the IC as possible and keep the traces short,
direct, and wide.
The traces between C
OUT3
, C
FF
, and FB are sensitive
to inductor magnetic-field interference. Route these
traces between ground planes or keep the traces away
from the inductor.
