74HC4050_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 6 of 13
NXP Semiconductors
74HC4050-Q100
Hex non-inverting HIGH-to-LOW level shifter
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
11. Waveforms
C
PD
power
dissipation
capacitance
C
L
=50pF;f=1 MHz;
V
I
=GNDtoV
CC
[3]
-14- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions T
amb
= 25 C T
amb
= 40 C
to +85 C
T
amb
= 40 C
to +125 C
Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. The input (nA) to output (nY) propagation delays
W
3/+
W
3+/
9
0
9
0
9
0
9
0
RXWSXW
$LQSXW
,
*1'
9
2+
9
2/
W
7/+
W
7+/
Table 8. Measurement points
Type Input Output
V
M
V
M
74HC4050-Q100 0.5V
CC
0.5V
CC
