ASM5P2305A, ASM5P2309A
3.3 V
Zero Delay
Buf
fer
Description
ASM5P2309A is a versatile, 3.3 V zero−delay buffer designed to
distribute high−speed clocks. It accepts one reference input and drives
out nine low−skew clocks. It is available in a 16−pin package. The
ASM5P2305A is the eight−pin version of the ASM5P2309A. It
accepts one reference input and drives out five low−skew clocks.
The −1H version of the ASM5P230xA operates at up to 133 MHz
frequencies, and has higher drive than the −1 devices. All parts have
on−chip PLLs that lock to an input clock on the REF. The PLL
feedback is on−chip and is obtained from the CLKOUT.
http://onsemi.com
ASM5P2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input Decoding
Table. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple ASM5P2309A and ASM5P2305A devices can accept the
same input clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than 700 pS.
All outputs have less than 200 pS of cycle−to−cycle jitter. The input
and output propagation delay is guaranteed to be less than ±350 pS,
and the output to output skew is guaranteed to be less than 200 pS.
The ASM5P2309A and the ASM5P2305A are available in two
different configurations, as shown in the ordering information table.
The ASM5P2305A−1 / ASM5P2309A−1 is the base part. The
ASM5P2305A−1H / ASM5P2309A−1H is the high drive version of
SOIC
−8
S
SUFFIX
CASE 751BD
SOIC
−16
S
SUFFIX
CASE 751BG
TSSOP
−8
T
SUFFIX
CASE 948AL
TSSOP−16
T
SUFFIX
CASE 948AN
the −1 and its rise and fall times are faster than −1 part.
PIN CONFIGURATIONS
1
Features
•
10 MHz to 133 MHz Operating Range, Compatible with CPU and
PCI Bus Frequencies
•
Zero Input−output Propagation Delay
•
Multiple Low−skew Outputs
♦
Output−output Skew less than 200 pS
♦
Device−device Skew less than 700 pS
♦
One Input Drives 9 Outputs, Grouped as
4 + 4 + 1 (ASM5P2309A)
♦
One Input Drives 5 Outputs (ASM5P2305A)
•
Less than 200 pS Cycle−to−Cycle Jitter is Compatible with
Pentium
®
Based Systems
•
Test Mode to Bypass PLL (ASM5P2309A Only, Refer to Select Input
Decoding Table)
•
Packaging Information:
ASM5P2309A: 16−pin SOIC, TSSOP
ASM5P2305A: 8−pin SOIC, TSSOP
•
Commercial and Industrial Temperature Range
•
3.3 V Operation
REF
CLK
CLK1
GND
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
ASM5P2305A
(Top View)
1
ASM5P2309A
(Top View)
CLKOUT
CLK4
V
DD
CLK3
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
•
Advanced 0.35
�
CMOS Technology
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 4
1 Publication Order Number:
ASM5P2305A/D
