ADP1712/ADP1713/ADP1714
Rev. A | Page 10 of 16
THEORY OF OPERATION
The ADP1712/ADP1713/ADP1714 are low dropout linear regula-
tors that use an advanced, proprietary architecture to provide high
power supply rejection ratio (PSRR) and excellent line and load
transient response with just a small 2.2 μF ceramic output capac-
itor. All devices operate from a 2.5 V to 5.5 V input rail and provide
up to 300 mA of output current. Incorporating a novel scaling
architecture, ground current is very low when driving light loads.
Ground current in the shutdown mode is typically less than 1 μA.
REFERENCE
CURRENT
LIMIT
THERMAL
PROTECT
SHUTDOWN
AND UVLO
GND
OUT
SS/
ADJ/
BYP/
TRK
IN
EN
06455-023
Figure 25. Internal Block Diagram
Internally, the ADP1712/ADP1713/ADP1714 each consist of a
reference, an error amplifier, a feedback voltage divider, and a
PMOS pass transistor. Output current is delivered via the PMOS
pass device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback volt-
age from the output and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the gate of the PMOS
device is pulled lower, which allows more current to pass and
increases the output voltage. If the feedback voltage is higher than
the reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to pass and decreasing the output voltage.
The ADP1712 is available in two versions, one with a fixed output
voltage and one with an adjustable output voltage. The fixed output
voltage is set internally to one of sixteen values between 0.75 V and
3.3 V, using an internal feedback network. The adjustable output
voltage can be set to between 0.8 V and 5.0 V by an external voltage
divider connected from OUT to ADJ. The ADP1713 and ADP1714
are available in fixed output voltage options only. The ADP1712
fixed version allows an external soft-start capacitor to be connected
between the SS pin and GND, which controls the output voltage
ramp during startup. The ADP1713 allows a reference bypass
capacitor to be connected between the BYP pin and GND, which
reduces output voltage noise and improves power supply rejection.
The ADP1714 features a track pin, which allows the output voltage
to follow the voltage at the TRK pin.
A logic on the EN pin determines if the output is active. When EN
is high, the output is on, and when EN is low, the output is off.
SOFT-START FUNCTION (ADP1712)
For applications that require a controlled startup, the ADP1712
provides a programmable soft-start function. Programmable soft
start is useful for reducing inrush current upon startup and for pro-
viding voltage sequencing. To implement soft start, connect a small
ceramic capacitor from SS to GND. Upon startup, a 1.2 μA current
source charges this capacitor. The ADP1712 start-up output voltage
is limited by the voltage at SS, providing a smooth ramp up to the
nominal output voltage. The soft-start time is calculated by
T
SS
= V
REF
×
(C
SS
/I
SS
) (1)
where:
T
SS
is the soft-start period.
V
REF
is the 0.8 V reference voltage.
C
SS
is the soft-start capacitance from SS to GND.
I
SS
is the current sourced from SS (1.2 μA).
When the ADP1712 is disabled (using EN), the soft-start capacitor
is discharged to GND through an internal 100 Ω resistor.
TIME (4ms/DIV)
2V/DI
V
1
2V/DI
V
2
EN
OUT
V
IN
= 5V
V
OUT
= 3.3V
C
OUT
= 2.2μF
C
SS
= 22nF
I
LOAD
= 300mA
0
6455-040
Figure 26. OUT Ramp-Up with External Soft-Start Capacitor
The ADP1712 adjustable version, ADP1713, and ADP1714 have
no pins for soft start, so the function is switched to an internal
soft-start capacitor. This sets the soft-start ramp-up period to
approximately 24 μs.
TIME (20µs/DIV)
2V/DI
V
1
1V/DI
V
2
EN
OUT
V
IN
= 5V
V
OUT
= 1.6V
C
OUT
= 2.2μF
I
LOAD
= 10mA
0
6455-041
Figure 27. OUT Ramp-Up with Internal Soft-Start
ADP1712/ADP1713/ADP1714
Rev. A | Page 11 of 16
ADJUSTABLE OUTPUT VOLTAGE
(ADP1712 ADJUSTABLE)
The ADP1712 adjustable version can have its output voltage
set over a 0.8 V to 5.0 V range. The output voltage is set by
connecting a resistive voltage divider from OUT to ADJ. The
output voltage is calculated using the equation
V
OUT
= 0.8 V (1 + R1/R2) (2)
where:
R1 is the resistor from OUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 100 nA, so for less
than 0.5% error due to the bias current, use values less than
60 kΩ for R2.
BYPASS CAPACITOR (ADP1713)
The ADP1713 allows for an external bypass capacitor to be
connected to the internal reference, which reduces output
voltage noise and improves power supply rejection. A low
leakage capacitor of 1 nF or greater (10 nF is recommended)
must be connected between the BYP and GND pins.
TRACK MODE (ADP1714)
The ADP1714 includes a tracking mode feature. As shown in
Figure 28, if the voltage applied at the TRK pin is less than the
nominal output voltage, OUT is equal to the voltage at TRK.
Otherwise, OUT regulates to its nominal output value.
For example, consider an ADP1714 with a nominal output
voltage of 3 V. If the voltage applied to its TRK pin is greater than
3 V, OUT maintains a nominal output voltage of 3 V. If the volt-
age applied to TRK is reduced below 3 V, OUT tracks this voltage.
OUT can track the TRK pin voltage from the nominal value all
the way down to 0 V. A voltage divider is present from TRK to the
error amplifier input with a divider ratio equal to the divider
from OUT to the error amplifier. This sets the output voltage
equal to the tracking voltage. Both divider ratios are set by post-
package trim, depending on the desired output voltage.
4
05
V
TRK
(V)
V
OUT
(V)
0
3
2
1
1234
06455-024
Figure 28. ADP1714 Output Voltage vs. Tracking Voltage
with Nominal Output Voltage Set to 3 V
ENABLE FEATURE
The ADP1712/ADP1713/ADP1714 use the EN pin to enable
and disable the OUT pin under normal operating conditions.
As shown in Figure 29, when a rising voltage on EN crosses the
active threshold, OUT turns on. When a falling voltage on EN
crosses the inactive threshold, OUT turns off.
TIME (4ms/DIV)
500mV/DI
V
EN
OUT
V
IN
=5V
V
OUT
=1.6V
C
OUT
=2.2μF
I
LOAD
=10mA
06455-025
1
Figure 29. ADP1712 Adjustable Typical EN Pin Operation
As can be seen, the EN pin has hysteresis built in. This prevents
on/off oscillations that can occur due to noise on the EN pin as
it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the IN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 30 shows typical EN active/inactive thresholds
when the input voltage varies from 2.5 V to 5.5 V.
1.4
0.5
2.50 5.50
V
IN
(V)
TYPICAL EN THRESHOLDS (V)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
EN INACTIVE
EN ACTIVE
HYSTERESIS
06455-026
Figure 30. Typical EN Pin Thresholds vs. Input Voltage
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP1712/ADP1713/ADP1714 have an undervoltage
lockout circuit, which monitors the voltage on the IN pin.
When the voltage on IN drops below 2 V (minimum), the
circuit activates, disabling the OUT pin.
ADP1712/ADP1713/ADP1714
Rev. A | Page 12 of 16
APPLICATION INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1712/ADP1713/ADP1714 are designed for operation
with small, space-saving ceramic capacitors, but they function
with most commonly used capacitors as long as care is taken about
the effective series resistance (ESR) value. The ESR of the output
capacitor affects stability of the LDO control loop. A minimum of
2.2 μF capacitance with an ESR of 500 mΩ or less is recommended
to ensure stability of the ADP1712/ADP1713/ADP1714. Transient
response to changes in load current is also affected by output
capacitance. Using a larger value of output capacitance improves
the transient response of the ADP1712/ADP1713/ADP1714 to
large changes in load current. Figure 31 and Figure 32 show the
transient responses for output capacitance values of 2.2 μF and
10 μF, respectively.
TIME (20μs/DIV)
20mV/DI
V
V
IN
= 5V
V
OUT
= 3.3V
C
IN
= 2.2µF
C
OUT
= 2.2µF
V
OUT
RESPONSE TO LOAD STEP
FROM 10mA TO 300mA
06455-027
Figure 31. Output Transient Response, C
OUT
= 2.2 μF
TIME (20μs/DIV)
20mV/DI
V
V
OUT
RESPONSE TO LOAD STEP
FROM 10mA TO 300mA
V
IN
= 5V
V
OUT
= 3.3V
C
IN
= 10µF
C
OUT
= 10µF
06455-028
Figure 32. Output Transient Response, C
OUT
= 10 μF
Input Bypass Capacitor
Connecting a 2.2 μF capacitor from the IN pin to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance are
encountered. If greater than 2.2 μF of output capacitance is
required, increasing the input capacitor to match is recommended.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1712/ADP1713/ADP1714, as long as they meet the
minimum capacitance and maximum ESR requirements.
Ceramic capacitors are manufactured with a variety of
dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temper-
ature range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V or 10 V are recommended. Y5V and
Z5U dielectrics are not recommended, due to their poor
temperature and dc bias characteristics.
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1712/ADP1713/ADP1714 are protected against damage
due to excessive power dissipation by current and thermal over-
load protection circuits. The ADP1712/ADP1713/ADP1714 are
designed to current limit when the output load reaches 500 mA
(typical). When the output load exceeds 500 mA, the output
voltage is reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation), when the junction temperature starts to rise
above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again and output
current is restored to its nominal value.
Consider the case where a hard short from OUT to ground occurs.
At first the ADP1712/ADP1713/ADP1714 current limit, so that
only 500 mA is conducted into the short. If self heating of the
junction is great enough to cause its temperature to rise above
150°C, thermal shutdown activates, turning off the output and
reducing the output current to zero. As the junction temper-
ature cools and drops below 135°C, the output turns on and
conducts 500 mA into the short, again causing the junction
temperature to rise above 150°C. This thermal oscillation
between 135°C and 150°C causes a current oscillation between
500 mA and 0 mA, which continues as long as the short
remains at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation needs to be externally
limited so junction temperatures do not exceed 125°C.

ADP1713AUJZ-3.3-R7

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators IC 300mA LDO CMOS
Lifecycle:
New from this manufacturer.
Delivery:
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