Table 15: Serial Presence-Detect EEPROM AC Operating Conditions (Continued)
Parameter/Condition Symbol Min Max Units Notes
SDA and SCL rise time
t
R
–
0.3 µs 2
SCL clock frequency
f
SCL
–
400 kHz
Data-in setup time
t
SU:DAT 100
–
ns
Start condition setup time
t
SU:STA 0.6
–
µs 3
Stop condition setup time
t
SU:STO 0.6
–
µs
WRITE cycle time
t
WRC
–
10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/
SPD.
1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
Serial Presence-Detect
PDF: 09005aef81a2f237
htf18c128_256x72fdy.pdf - Rev. D 12/09 EN
10
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© 2005 Micron Technology, Inc. All rights reserved.
