MT18HTF12872FDY-667B5E3

General Description
Micron’s FBDIMM devices adhere to the currently proposed industry specifications for
FBDIMMs. The following specifications contain detailed information on FBDIMM de-
sign, interfaces, and theory of operation and are listed here for the system designers’
convenience. Refer to the JEDEC Web site for available specifications.
FBDIMM Design Specification – pending JEDEC approval
FBDIMM: Architecture and Protocol – JESD206
FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20
Design for Test, Design for Validation (DFx) Specification
Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C,
page 4.1.2.7-1
This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that
has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from
the channel behind an AMB buffer on the FBDIMM. Memory device capacity remains
high, and total memory capacity scales with DDR2 SDRAM bit density.
As shown in the System Block Diagram, the FBDIMM channel provides a communica-
tion path from a host controller to an array of DDR2 SDRAM devices, with the DDR2
SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2
SDRAM devices from the channel enhances the communication path and significantly
increases the reliability and availability of the memory subsystem.
Advanced Memory Buffer
The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB
component, located in the center of each FBDIMM, acts as a repeater and buffer for all
signals and commands exchanged between the host controller and DDR2 SDRAM devi-
ces, including data input and output. The AMB communicates with the host controller
and adjacent FBDIMMs on a system board using an industry-standard, high-speed, dif-
ferential, 1.5V, point-to-point interface. The AMB also enables buffering of memory
traffic to support large memory capacities. Refer to the JEDEC JESD82-20 specification
for further information.
I
DD
Conditions and Specifications
Table 7: I
DD
Conditions
Symbol Condition
I
DD_IDLE_0
Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel ena-
bled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2
SDRAM clock active
I
DD_IDLE_1
Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels
enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
I
DD_ACTIVE_1
Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secon-
dary channels enabled; DDR2 SDRAM clock active; CKE HIGH
I
DD_ACTIVE_2
Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream
DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM
clock active; CKE HIGH; Command and address lines stable
1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
General Description
PDF: 09005aef81a2f237
htf18c128_256x72fdy.pdf - Rev. D 12/09 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2005 Micron Technology, Inc. All rights reserved.
Table 7: I
DD
Conditions (Continued)
Symbol Condition
I
DD_TRAINING
Training: Primary and secondary channels enabled; 100% toggle on all channel lanes;
DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM
clock active
I
DD_IBIST
IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secon-
dary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
I
DD_EI
Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel
disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and
CKE driven LOW
Note:
1. Actual test conditions may vary from published JEDEC test conditions.
Table 8: I
DD
Specifications – 1GB DDR2-533
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2200 3000 3400 3200 3500 3800 2000 A
I
DD
1420 1420 2545 1420 1420 1420 326 A
Total power 6.2 7.4 10.2 7.7 8.2 8.7 3.8 W
Table 9: I
DD
Specifications – 1GB DDR2-667
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2600 3400 3900 3700 4000 4500 2500 A
I
DD
1510 1510 2777 1510 1510 1510 326 A
Total power 7.0 8.2 11.4 8.7 9.2 10.0 4.6 W
Table 10: I
DD
Specifications – 1GB DDR2-800
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
TBD TBD TBD TBD TBD TBD TBD A
I
DD
TBD TBD TBD TBD TBD TBD TBD A
Total power TBD TBD TBD TBD TBD TBD TBD W
Table 11: I
DD
Specifications – 2GB DDR2-533
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2200 3000 3400 3200 3500 3800 2000 A
I
DD
1420 1420 2425 1420 1420 1420 326 A
Total power 6.2 7.4 10.0 7.7 8.2 8.7 3.8 W
1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
I
DD
Conditions and Specifications
PDF: 09005aef81a2f237
htf18c128_256x72fdy.pdf - Rev. D 12/09 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2005 Micron Technology, Inc. All rights reserved.
Table 12: I
DD
Specifications – 2GB DDR2-667
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2600 3400 3900 3700 4000 4500 2500 A
I
DD
1420 1420 2515 1420 1420 1420 326 A
Total power 6.8 8.1 11.0 8.5 9.0 9.8 4.6 W
Table 13: I
DD
Specifications – 12B DDR2-800
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
TBD TBD TBD TBD TBD TBD TBD A
I
DD
TBD TBD TBD TBD TBD TBD TBD A
Total power TBD TBD TBD TBD TBD TBD TBD W
Note:
1. Total power is based on maximum voltage levels, I
CC
at 1.575V and I
DD
at 1.9V.
Serial Presence-Detect
Table 14: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition Symbol Min Max Units
EEPROM and AMB supply voltage V
DDSPD
3 3.6 V
Input high voltage: Logic 1; all inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: Logic 0; all inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.10 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 15: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3
µs
Data-out hold time
t
DH 200
ns
SDA and SCL fall time
t
F
300 ns 2
Data-in hold time
t
HD:DAT 0
µs
Start condition hold time
t
HD:STA 0.6
µs
Clock HIGH period
t
HIGH 0.6
µs
Noise suppression time constant at SCL, SDA inputs
t
I
50 ns
Clock LOW period
t
LOW 1.3
µs
1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
Serial Presence-Detect
PDF: 09005aef81a2f237
htf18c128_256x72fdy.pdf - Rev. D 12/09 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2005 Micron Technology, Inc. All rights reserved.

MT18HTF12872FDY-667B5E3

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 1GB 240FBDIMM
Lifecycle:
New from this manufacturer.
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