4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
09005aef8114a789 Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45.fm - Rev. E 6/04 EN
4 ©2003 Micron Technology, Inc. All rights reserved.
Table 1: Pin Descriptions
44-PIN
SOP
NUMBERS
40-PIN
TSOP
NUMBERS
48-PIN
TSOP
NUMBERS SYMBOL TYPE DESCRIPTION
43 9 11 WE# Input
Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
21214WP#Input
Write Protect: Unlocks the boot block when HIGH if VPP
=
VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a
WRITE or ERASE. Does not affect WRITE or ERASE
operation on other blocks.
12 22 26 CE# Input
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
44 10 12 RP# Input
Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot
block and
overrides the condition of WP# when at V
HH (12V), and
must be held at V
IH during all other modes of operation.
14 24 28 OE# Input
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
33 – 47 BYTE# Input
Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-
Z, and all data is accessed through DQ0–DQ7. DQ15/(A-1)
becomes the least significant address input.
11, 10, 9, 8,
7, 6, 5, 4,
42, 41, 40,
39, 38, 37,
36, 35, 34, 3
21, 20, 19,
18, 17, 16,
15, 14, 8, 7,
36, 6, 5, 4,
3, 2, 1, 40,
13
25, 24, 23,
22, 21, 20,
19, 18, 8, 7,
6, 5, 4, 3, 2,
1, 48, 17
A0–A17/
(A18)
Input
Address Inputs: Select a unique, 16-bit word or 8-bit byte.
The DQ15/(A-1) input becomes the lowest order address
when BYTE# = LOW (MT28F400B3) to allow for a selection
of an 8-bit byte from the 524,288 available.
31 – 45 DQ15/
(A-1)
Input/
Output
Data I/O: MSB of data when BYTE# = HIGH. Address Input:
LSB of address input when BYTE# = LOW during READ or
WRITE operation.
15, 17, 19,
21, 24, 26,
28, 30
25-28, 32-35 29, 31, 33,
35, 38, 40,
42, 44
DQ0–DQ7 Input/
Output
Data I/Os: Data output pins during any READ operation or
data input pins during a WRITE. These pins are used to
inputcommands to the CEL.
16, 18, 20,
22, 25, 27,
29
– 30, 32, 34,
36, 39, 41,
43
DQ8–
DQ14
Input/
Output
Data I/Os: Data output pins during any READ operation or
data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
11113
VPP
Supply
Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH1 (3.3V) or VPPH2 (5V). VPP = “Don’t
Care”
during all other operations.
23 30, 31 37
VCC
Supply
Power Supply: +3.3V ±0.3V.
13, 32 23, 39 27, 46 V
SS Supply
Ground.
– 29, 37, 38 9, 10, 15, 16 NC –
No Connect: These pins may be driven or left unconnected.