List of figures L9777
4/25 DocID13496 Rev 4
List of figures
Figure 1. Block diagram (option A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Package pin configuration (options A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Block diagram (option B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Package pin configuration (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6. VCC versus output current IVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Filter time between VCC and NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Filter time between NMI and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. RESET and NMI drivers fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11. Resistor divider to adjust the under voltage threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Watchdog timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. VDD_LOW filter time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. PowerSSO-12 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 23
DocID13496 Rev 4 5/25
L9777 Block diagrams and pins configuration
24
1 Block diagrams and pins configuration
1.1 Block diagram (option A)
Figure 1. Block diagram (option A)
1.2 Option B features
VDD can sustain short to 40 V regardless of VI battery voltage
Current capability of VDD scaled down to 50 mA with dropout of 1.5 V (Max.)
In default condition, VDD and WD functions are disabled using 2 pull down current on
VDD_EN and WD_EN pin
Standby current consumption reduced to 100 μA (Typ.)
Figure 2. Package pin configuration (options A and B)
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Block diagrams and pins configuration L9777
6/25 DocID13496 Rev 4
Figure 3. Block diagram (option B)
Figure 4. Block diagram (option C)
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L9777C

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
LDO Voltage Regulators Low-Power Voltage Regulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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