NCV7344
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10
Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
ISO 11898−2:2016 Specification NCV7344
Datasheet
Parameter Notation Symbol
Dominant output characteristics
Single ended voltage on CAN_H V
CAN_H
V
o(dom)(CANH)
Single ended voltage on CAN_L V
CAN_L
V
o(dom)(CANL)
Differential voltage on normal bus load V
Diff
V
o(dom)(diff)
Differential voltage on effective resistance during arbitration V
Diff
V
o(dom)(diff)_arb
Differential voltage on extended bus load range (optional) V
Diff
V
o(dom)(diff)
Driver symmetry
Driver symmetry V
SYM
V
o(dom)(sym)
Driver output current
Absolute current on CAN_H I
CAN_H
I
o(SC)(CANH)
Absolute current on CAN_L I
CAN_L
I
o(SC)(CANL)
Receiver output characteristics, bus biasing active
Single ended output voltage on CAN_H V
CAN_H
V
o(rec)(CANH)
Single ended output voltage on CAN_L V
CAN_L
V
o(rec)(CANL)
Differential output voltage V
Diff
V
o(rec)(diff)
Receiver output characteristics, bus biasing inactive
Single ended output voltage on CAN_H V
CAN_H
V
o(off)(CANH)
Single ended output voltage on CAN_L V
CAN_L
V
o(off)(CANL)
Differential output voltage V
Diff
V
o(off)(diff)
Optional transmit dominant timeout
Transmit dominant timeout, long t
dom
t
dom(TxD)
Transmit dominant timeout, short t
dom
NA
Static receiver input characteristics, bus biasing active
Recessive state differential input voltage range V
Diff
V
i(rec)(diff)_NM
Dominant state differential input voltage range V
Diff
V
i(dom)(diff)_NM
Static receiver input characteristics, bus biasing inactive
Recessive state differential input voltage range V
Diff
V
i(rec)(diff)_LP
Dominant state differential input voltage range V
Diff
V
i(dom)(diff)_LP
Receiver input resistance
Differential internal resistance R
Diff
R
i(diff)
Single ended internal resistance R
CAN_H
R
CAN_L
R
i(cm)(CANH)
R
i(cm)(CANL)
Receiver input resistance matching
Matching a of internal resistance m
R
R
i(cm)(m)
Implementation loop delay requirement
Loop delay t
Loop
t
pd_rd
t
pd_dr
Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s t
Bit(Bus)
t
Bit(Vi(diff))
Received recessive bit width @ 2 Mbit/s t
Bit(RXD)
t
Bit(RxD)