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TJA1048T,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 6 — 19 March 2018 7 of 27
NXP Semiconductors
TJA1048
Dual high-speed CAN transceiver with Standby mode
The complete dominant-recessive-dominant pattern must be received within t
to(wake)bus
to
be recognized as a valid wake-up pattern (see Figure 4
). Pin RXD1/RXD2 will remain
recessive until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJA1048 will remain in Standby mode
with the bus signals reflected on RXD1/RXD2. Note that dominant or recessive phases
lasting less than t
fltr(wake)bus
will not be detected by the low-power differential receiver and
will not be reflected on RXD1/RXD2 in Standby mode.
A wake-up event will not be registered if any of the following events occurs while a
wake-up sequence is being transmitted:
• The TJA1048 switches to Normal mode
• The complete wake-up pattern was not received within t
to(wake)bus
• A V
IO
undervoltage is detected (V
IO
< V
uvd(VIO)
; see Section 7.2.3)
If any of these events occurs while a wake-up sequence is being received, the internal
wake-up logic will be reset and the complete wake-up sequence will have to be
re-transmitted to trigger a wake-up event.
7.2 Fail-safe features
7.2.1 TXD dominant time-out function
A 'TXD dominant time-out' timer is started when pin TXD1/TXD2 is set LOW. If the LOW
state on this pin persists for longer than t
to(dom)TXD
, the transmitter is disabled, releasing
the bus lines to recessive state. This function prevents a hardware and/or software
application failure from driving the bus lines to a permanent dominant state (blocking all
network communications). The TXD dominant time-out timer is reset when pin
TXD1/TXD2 is set HIGH. The TXD dominant time-out time also defines the minimum
possible bit rate of 40 kbit/s. The TJA1048 has two TXD dominant time-out timers that
operate independently of each other.
Fig 4. Wake-up timing
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IOWUZDNHEXV
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TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 6 — 19 March 2018 8 of 27
NXP Semiconductors
TJA1048
Dual high-speed CAN transceiver with Standby mode
7.2.2 Internal biasing of TXD1, TXD2, STBN1 and STBN2 input pins
Pins TXD1 and TXD2 have internal pull-ups to V
IO
and pins STBN1 and STBN2 have
internal pull-downs to GNDA and GNDB. This ensures a safe, defined state if any of these
pins is left floating. Pins GNDA and GNDB must be connected together in the application.
Pull-up/pull-down currents flow in these pins in all states. Pins TXD1 and TXD2 should be
held HIGH in Standby mode to minimize the supply current; pins STBN1 and STBN2
should be held LOW.
7.2.3 Undervoltage detection on pins V
CC
and V
IO
Should V
CC
drop below the V
CC
undervoltage detection level, V
uvd(VCC)
, both transceivers
will switch to Standby mode. The logic state of pins STBN1 and STBN2 will be ignored
until V
CC
has recovered.
Should V
IO
drop below the V
IO
undervoltage detection level, V
uvd(VIO)
, the transceivers will
switch off and disengage from the bus (zero load) until V
IO
has recovered.
7.2.4 Overtemperature protection
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, T
j(sd)
, both output drivers will be
disabled. When the virtual junction temperature drops below T
j(sd)
again, the output
drivers will recover independently once TXD1/TXD2 has been reset to HIGH. Including
the TXD1/TXD2 condition prevents output driver oscillation due to small variations in
temperature.
7.3 V
IO
supply pin
Pin V
IO
should be connected to the microcontroller supply voltage (see Figure 7). This will
adjust the signal levels of pins TXD1, TXD2, RXD1, RXD2, STBN1 and STBN2 to the I/O
levels of the microcontroller. Pin V
IO
also provides the internal supply voltage for the
transceiver’s low-power differential receiver. For applications running in low-power mode,
this allows the bus lines to be monitored for activity even if there is no supply voltage on
pin V
CC
.
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 6 — 19 March 2018 9 of 27
NXP Semiconductors
TJA1048
Dual high-speed CAN transceiver with Standby mode
8. Limiting values
[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2] According to IEC TS 62228 (2007), Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2: 2004-06.
[3] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[4] According to AEC-Q100-002.
[5] According to AEC-Q100-003.
[6] According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T
vj
=T
amb
+P R
th(vj-a)
, where R
th(vj-a)
is a
fixed value to be used for the calculation of T
vj
. The rating for T
vj
limits the allowable combinations of power dissipation (P) and ambient
temperature (T
amb
).
9. Thermal characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter Conditions Min Max Unit
V
x
voltage on pin x
[1]
on pins CANH1, CANL1, CANH2 and CANL2 58 +58 V
on any other pin 0.3 +7 V
V
(CANH-CANL)
voltage between pin CANH
and pin CANL
27 +27 V
V
trt
transient voltage on pins CANH1, CANL1, CANH2 and CANL2
[2]
pulse 1 100 - V
pulse 2a - 75 V
pulse 3a 150 - V
pulse 3b - 100 V
V
ESD
electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 )
[3]
on pins CANH1, CANL1, CANH2 and CANL2 6+6 kV
Human Body Model (HBM); 100 pF, 1.5 k
[4]
on pins CANH1, CANL1, CANH2 and CANL2 6+6 kV
at any other pin 4+4 kV
Machine Model (MM); 200 pF, 0.75 H, 10
[5]
at any pin 300 +300 V
Charged Device Model (CDM); field Induced
charge; 4 pF
[6]
at corner pins 750 +750 V
at any pin 500 +500 V
T
vj
virtual junction temperature
[7]
40 +150 C
T
stg
storage temperature 55 +150 C
Table 6. Thermal characteristics
Values determined for free convection conditions on a JESD51-7 board.
Symbol Parameter Conditions Value Unit
R
th(vj-a)
thermal resistance from virtual junction to
ambient
SO14 65 K/W
HVSON14 42 K/W
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TJA1048T,112

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Buy TJA1048T,112
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC DL HI-SP CAN TRNSCVR W/ STANDBY MODE
Lifecycle:
New from this manufacturer.
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