89H24NT6AG2ZCHLG Datasheet 89H24NT6AG2ZCHLG, 89H24NT6AG2ZBHLG, 89H24NT24G2ZBHLG | P7-P9

IDT 89HPES24NT6AG2 Datasheet

7 of 34 December 17, 2013

GPIO[3] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART3PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

2nd Alternate function pin name: P4ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 4 Link Active Status Output.

GPIO[4] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: FAILOVER0

1st Alternate function pin type: Input

1st Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

2nd Alternate function pin name: P0LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 0 Link Up Status output.

GPIO[5] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: GPEN

1st Alternate function pin type: Output

1st Alternate function: Hot-plug general purpose even output.

2nd Alternate function pin name: P0ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 0 Link Active Status Output.

GPIO[6] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: FAILOVER1

1st Alternate function pin type: Input

1st Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

2nd Alternate function pin name: FAILOVER3

2nd Alternate function pin type: Input

2nd Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: FAILOVER2

1st Alternate function pin type: Input

1st Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

2nd Alternate function pin name: P8LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 8 Link Up Status output.

GPIO[8] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: IOEXPINTN

1st Alternate function pin type: Input

1st Alternate function: IO expander interrupt.

2nd Alternate function pin name: P8ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 8 Link Active Status Output.

Signal Type Name/Description

Table 5 General Purpose I/O Pins (Part 2 of 2)

IDT 89HPES24NT6AG2 Datasheet

8 of 34 December 17, 2013

Signal Type Name/Description

STK0CFG[0] I Stack 0 Configuration. This pin selects the configuration of stack 0.

STK1CFG[0] I Stack 1 Configuration. This pin selects the configuration of stack 1.

STK2CFG[0] I Stack 2 Configuration. This pin selects the configuration of stack 2.

Table 6 Stack Configuration Pins

Signal Type Name/Description

CLKMODE[1:0] I Clock Mode. These signals determine the port clocking mode used by ports of the

device.

GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of the GCLKP

and GCLKN signals.

0x0 100 MHz

0x1 125 MHz

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the device.

RSTHALT I Reset Halt. When this signal is asserted during a switch fundamental reset sequence,

the switch remains in a quasi-reset state with the Master and Slave SMBuses active.

This allows software to read and write registers internal to the device before normal

device operation begins. The device exits the quasi-reset state when the RSTHALT bit

is cleared in the SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the switch operating mode.

These pins should be static and not change following the negation of PERSTN.

0x0 - Single partition

0x1 - Single partition with Serial EEPROM initialization

0x2 - Single partition with Serial EEPROM Jump 0 initialization

0x3 - Single partition with Serial EEPROM Jump 1 initialization

0x4 through 0x7 - Reserved

0x8 - Single partition with reduced latency

0x9 - Single partition with Serial EEPROM initialization and reduced latency

0xA - Multi-partition with Unattached ports

0xB - Multi-partition with Unattached ports and I

C Reset

0xC - Multi-partition with Unattached ports and Serial EEPROM initialization

0xD - Multi-partition with Unattached ports with I

C Reset and Serial EEPROM initial-

ization

0xE - Multi-partition with Disabled ports

0xF - Multi-partition with Disabled ports and Serial EEPROM initialization

Table 7 System Pins

IDT 89HPES24NT6AG2 Datasheet

9 of 34 December 17, 2013

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of

the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system

clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG

Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or

JTAG Controller. When no data is being shifted out, this signal is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary

scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic

and JTAG TAP Controller. An external pull-up on the board is recommended to meet

the JTAG specification in cases where the tester can access this signal. However, for

systems running in functional mode, one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 8 Test Pins

Signal Type Name/Description

REFRES[5:0] Analog External Reference Resistor. Reference for the corresponding SerDes

bias currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should

be connected from this pin to ground and isolated from any source of noise

injection. Each bit of this signal corresponds to a SerDes quad, e.g.,

REFRES[5] is the reference resistor for SerDes quad 5.

REFRESPLL Analog PLL External Reference Resistor. Provides a reference for the PLL bias

currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be

connected from this pin to ground and isolated from any source of noise

injection.

CORE I Core V

DD.

Power supply for core logic (1.0V).

I/O I I/O V

DD.

LVTTL I/O buffer power supply (3.3V).

PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).

PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).

PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

power supply (1.0V).

I Ground.

Table 9 Power, Ground, and SerDes Resistor Pins

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

89H24NT6AG2ZCHLG

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