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89H24NT6AG2ZCHLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
IDT 89HPES24NT6AG2 Datasheet
10 of 34 December 17, 2013
Pin Characteristics
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to
appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, floating
pins can cause a slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally, No Connection pins
should not be connected.
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
PCI Express Interface PE00RN[3:0] I PCIe
differential
2
Serial Link Note: Unused SerDes
pins can be left floating
PE00RP[3:0] I
PE00TN[3:0] O
PE00TP[3:0] O
PE02RN[3:0] I
PE02RP[3:0] I
PE02TN[3:0] O
PE02TP[3:0] O
PE04RN[3:0] I
PE04RP[3:0] I
PE04TN[3:0] O
PE04TP[3:0] O
PE06RN[3:0] I
PE06RP[3:0] I
PE06TN[3:0] O
PE06TP[3:0] O
PE08RN[3:0] I
PE08RP[3:0] I
PE08TN[3:0] O
PE08TP[3:0] O
PE12RN[3:0] I
PE12RP[3:0] I
PE12TN[3:0] O
PE12TP[3:0] O
Reference Clocks GCLKN[1:0] I HCSL Diff. Clock
Input
Refer to Table 11
Note: Unused port
clock pins should be
connected to Vss on
the board.
GCLKP[1:0] I
P00CLKN I
P00CLKP I
P02CLKN I
P02CLKP I
P04CLKN I
Table 10 Pin Characteristics (Part 1 of 2)
IDT 89HPES24NT6AG2 Datasheet
11 of 34 December 17, 2013
Reference Clocks (cont.) P04CLKP I HCSL Diff. Clock
Input
Refer to Table 11
P06CLKN I
P06CLKP I
P08CLKN I
P08CLKP I
P12CLKN I
P12CLKP I
SMBus MSMBCLK I/O LVTTL STI
3
Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specifica-
tion.
MSMBDAT I/O STI
SSMBADDR[2,1] I pull-up
SSMBCLK I/O STI Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specifica-
tion.
SSMBDAT I/O STI
General Purpose I/O GPIO[8:0] I/O LVTTL STI, High
Drive
pull-up Unused pins can be left
floating.
Stack Configuration STK0CFG[0] I LVTTL Input pull-down Unused pins can be left
floating.
STK1CFG[0] I pull-down
STK2CFG[0] I pull-down
System Pins CLKMODE[1:0] I LVTTL Input pull-up Unused pins can be left
floating.
GCLKFSEL I pull-down
PERSTN I Schmitt trigger
RSTHALT I pull-down Unused pins can be left
floating.
SWMODE[3:0] I pull-down
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up Unused pins can be left
floating.
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
SerDes Reference Resis-
tors
REFRES[5:0] Analog Unused pins should be
connected to Vss on
the board.
REFRESPLL
1.
Internal resistor values under typical operating conditions are 92K for pull-up and 91K for pull-down.
2.
All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
Schmitt Trigger Input (STI).
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 10 Pin Characteristics (Part 2 of 2)
IDT 89HPES24NT6AG2 Datasheet
12 of 34 December 17, 2013
Logic Diagram — PES24NT6AG2
Figure 3 PES24NT6AG2 Logic Diagram
JTAG_TCK
GPIO[8:0]
9
General Purpose
I/O
MSMBCLK
MSMBDAT
Master
SMBus Interface
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
P00CLKN
P00CLKP
PE00RP[3:0]
PE00RN[3:0]
PE00TP[3;0]
PE00TN[3:0]
PE02TP[3:0]
PE02TN[3:0]
PES24NT6AG2
2
PCIe Switch
SerDes Input
Port 0
PCIe Switch
SerDes Output
Port 2
PCIe Switch
SerDes Output
Port 0
Global
Reference Clocks
GCLKN[1:0]
GCLKP[1:0]
GCLKFSEL
V
DD
CORE
V
DD
I/O
V
DD
PEA
Power/Ground
V
SS
V
DD
PEHA
V
DD
PETA
RSTHALT
System
Pins
SWMODE[3:0]
4
CLKMODE[1:0]
PERSTN
2
SSMBCLK
SSMBDAT
Slave
SMBus Interface
SSMBADDR[2,1]
STK0CFG[0]
STK1CFG[0]
STK2CFG[0]
Stack
Configuration
REFRES[5:0]
SerDes
Reference
Resistors
REFRESPLL
P02CLKN
P02CLKP
PE02RP[3:0]
PE02RN[3:0]
PCIe Switch
SerDes Input
Port 2
P04CLKN
P04CLKP
PE04RP[3:0]
PE04RN[3:0]
PCIe Switch
SerDes Input
Port 4
P06CLKN
P06CLKP
PE06RP[3:0]
PE06RN[3:0]
PCIe Switch
SerDes Input
Port 6
P08CLKN
P08CLKP
PE08RP[3:0]
PE08RN[3:0]
PCIe Switch
SerDes Input
Port 8
P12CLKN
P12CLKP
PE12RP[3:0]
PE12RN[3:0]
PCIe Switch
SerDes Input
Port 12
PE04TP[3:0]
PE04TN[3:0]
PCIe Switch
SerDes Output
Port 4
PE06TP[3:0]
PE06TN[3:0]
PCIe Switch
SerDes Output
Port 6
PE08TP[3:0]
PE08TN[3:0]
PCIe Switch
SerDes Output
Port 8
PE12TP[3:0]
PE12TN[3:0]
PCIe Switch
SerDes Output
Port 12
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

89H24NT6AG2ZCHLGI

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PCI Interface IC PCIE SWITCH
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