89H24NT6AG2ZCHLGI Datasheet 89H24NT6AG2ZCHLG, 89H24NT6AG2ZBHLG, 89H24NT24G2ZBHLG | P4-P6

IDT 89HPES24NT6AG2 Datasheet

4 of 34 December 17, 2013

Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and

SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration. In the split configuration, the

master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not

support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM

and I/O expander slaves.

Figure 2 Split SMBus Interface Configuration

Hot-Plug Interface

The PES24NT6AG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the

PES24NT6AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset

and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES24NT6AG2 generates an SMBus transaction to the I/O

expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on

the IOEXPINTN input pin (alternate function of GPIO) of the PES24NT6AG2. In response to an I/O expander interrupt, the PES24NT6AG2 generates

an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES24NT6AG2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose

outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus

slave interface, or serial configuration EEPROM.

Pin Description

The following tables list the functions of the pins provided on the PES24NT6AG2. Some of the functions listed may be multiplexed onto the same

pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero

(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal

ending in “N” is the negative portion of the differential pair.

Note: Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.

Processor

Switch

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

...

Hot-Plug

I/O

Expander

IDT 89HPES24NT6AG2 Datasheet

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Signal Type Name/Description

PE00RN[3:0]

PE00RP[3:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for

port 0.

PE00TN[3:0]

PE00TP[3:0]

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for

port 0.

PE02RN[3:0]

PE02RP[3:0]

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for

port 2.

PE02TN[3:0]

PE02TP[3:0]

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for

port 2.

PE04RN[3:0]

PE04RP[3:0]

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for

port 4.

PE04TN[3:0]

PE04TP[3:0]

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for

port 4.

PE06RN[3:0]

PE06RP[3:0]

I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for

port 6.

PE06TN[3:0]

PE06TP[3:0]

O PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for

port 6.

PE08RN[3:0]

PE08RP[3:0]

I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pair for

port 8.

PE08TN[3:0]

PE08TP[3:0]

O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pair for

port 8.

PE12RN[3:0]

PE12RP[3:0]

I PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pair for

port 12.

PE12TN[3:0]

PE12TP[3:0]

O PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pair for

port 12.

Table 2 PCI Express Interface Pins

Signal Type Name/Description

GCLKN[1:0]

GCLKP[1:0]

I Global Reference Clock. Differential reference clock input pairs. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic. The frequency of the differential reference

clock is determined by the GCLKFSEL signal.

Note: Both pairs of the Global Reference Clocks must be connected to and

derived from the same clock source. Refer to the Overview section of

Chapter 2 in the PES24NT6AG2 User Manual for additional details.

P00CLKN

P00CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 0.

P02CLKN

P02CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 2.

P04CLKN

P04CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 4.

Table 3 Reference Clock Pins (Part 1 of 2)

IDT 89HPES24NT6AG2 Datasheet

6 of 34 December 17, 2013

P06CLKN

P06CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 6.

P08CLKN

P08CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 8.

P12CLKN

P12CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 12.

Signal Type Name/Description

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the

master SMBus. It is active and generating the clock only when the EEPROM or I/O

Expanders are being accessed.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus.

SSMBADDR[2,1] I Slave SMBus Address. These pins determine the SMBus address to which the slave

SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the

slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.

Table 4 SMBus Interface Pins

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART0PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART1PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART2PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

2nd Alternate function pin name: P4LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 4 Link Up Status output.

Table 5 General Purpose I/O Pins (Part 1 of 2)

Signal Type Name/Description

Table 3 Reference Clock Pins (Part 2 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

89H24NT6AG2ZCHLGI

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