REVISION 9 3/15/16 6 ©2016 Integrated Device Technology, Inc.
MPC9447 DATA SHEET
APPLICATION INFORMATION
Figure 3. Output Clock Stop (CLK_STOP)
Timing Diagram
Driving Transmission Lines
The MPC9447 clock driver was designed to drive high-speed
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were designed
to exhibit the lowest impedance possible. With an output impedance
of 17 (V
CC
= 3.3 V), the outputs can drive either parallel or series
terminated transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note AN1091.
In most high performance clock networks, point-to-point distribution
of signals is the method of choice. In a point-to-point scheme, either
series terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of the
line with a 50 resistance to V
CC
2.
Figure 4. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current, and thus,
only a single terminated line can be driven by each output of the
MPC9447 clock driver. For the series terminated case, however,
there is no DC current draw; thus, the outputs can drive multiple
series terminated lines. Figure 4 illustrates an output driving a single
series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9447 clock driver
is effectively doubled due to its capability to drive multiple lines at
V
CC
= 3.3 V.
Figure 5. Single versus Dual Line
Termination Waveforms
The waveform plots in Figure 5 show the simulation results of an
output driving a single line versus two lines. In both cases, the drive
capability of the MPC9447 output buffer is more than sufficient to
drive 50 transmission lines on the incident edge. Note from the
delay measurements in the simulation,s a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9447. The output waveform in
Figure 5 shows a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 33 series resistor, plus the output impedance,
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
V
L
=V
S
(Z
0
(R
S
+R
0
+Z
0
))
Z
0
= 50 || 50
R
S
= 33 || 33
R
0
= 17
V
L
= 3.0 (25 (16.5+17+25)
= 1.28 V
At the load end, the voltage will double, due to the near unity
reflection coefficient, to 2.5 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
CCLK0 or
CCLK1
CLK_STOP
Q0 to Q8
17
IN
MPC9447
Output
Buffer
R
S
= 33
Z
O
= 50
OutA
17
IN
MPC9447
Output
Buffer
R
S
= 33
Z
O
= 50
OutB0
R
S
= 33
Z
O
= 50
OutB1
Time (ns)
Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
