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MPC9447AC

P1-P3P4-P6P7-P9P10-P11
REVISION 9 3/15/16 7 3.3V, 2.5V, 1:9 LVCMOS CLOCK FANOUT BUFFER
MPC9447 DATA SHEET
Since this step is well above the threshold region, it will not cause
any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better match
the impedances when driving multiple lines, the situation in Figure 6
should be used. In this case, the series terminating resistors are
reduced such that when the parallel combination is added to the
output buffer impedance, the line impedance is perfectly matched.
Figure 6. Optimized Dual Line Termination
The Following Figures Illustrate the Measurement Reference for the MPC9447 Clock Driver Circuit
Figure 7. CCLK MPC9447 AC Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9447 DUT
V
TT
V
TT
REVISION 9 3/15/16 8 ©2016 Integrated Device Technology, Inc.
MPC9447 DATA SHEET
Figure 8. Propagation Delay (t
PD
) Test Reference
Figure 9. Output-to-Output Skew t
SK(LH, HL)
Figure 10. Output Pulse Skew (t
SK(P)
) Test Reference
Figure 11. Output Duty Cycle (DC)
Figure 12. Output Transition Time Test Reference
Figure 13. Cycle-to-Cycle Jitter
Figure 14. Setup and Hold Time (t
S
, t
H
) Test Reference
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
CCLK
Q
X
t
P(LH)
t
P(HL)
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a single
device.
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
SK(LH)
t
SK(HL)
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
P(LH)
CCLK
Q
X
t
P(HL)
t
SK(P)
= | t
PLH
– t
PHL
|
The time from the output controlled edge to the non-controlled edge,
divided by the time between output controlled edges, expressed as
a percentage.
V
CC
V
CC
2
GND
t
P
T
0
DC = (t
P ?
T
0
x 100%)
t
F
t
R
V
CC
=3.3 V V
CC
=2.5 V
2.4 1.8 V
0.55 0.6 V
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
T
N
T
JIT(CC)
= |T
N
-T
N+1
|
T
N+1
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
S
CCLK
PCLK
CLK_STOP
t
H
PACKAGE DIMENSIONS
MPC9447 REVISION 9 3/15/16 9 ©2016 Integrated Device Technology, Inc.
MPC9447 Data Sheet 3.3V, 2.5V, 1:9 LVCMOS CLOCK FANOUT BUFFER
12 REF
DIM MIN MAX
MILLIMETERS
A
A1
7.00 BSC
A2
0.80 BSC
b
9.00 BSC
b1 0.30 0.40
c 0.09 0.20
c1 0.09 0.16
D
D1
e
E
E1
L
L1
1.00 REF
R1 0.08 0.20
R2
S
1
1.40 1.60
0.05 0.15
1.35 1.45
0.30 0.45
0.08 ---
0˚ 7˚
9.00 BSC
7.00 BSC
0.50 0.70
q
q
0.20 REF
D1
D/2
EE1
1
8
9
17
25
32
D1/2
E1/2
E/2
4X
D
7
A
D
B
A-B0.20
H D
4X
A-B0.20 C D
6
6
4
4
DETAIL G
PIN 1 INDEX
DETAIL AD
R R2
θ˚
(S)
L
(L1)
0.25
GAUGE PLANE
A2
A
A1
(θ1˚)
8X
R R1
e
SEATING
PLANE
DETAIL AD
0.1 C
C
32X
28X
H
DETAIL G
F
F
e/2
A, B, D
3
SECTION F-F
BASE
c1c
b
b1
METAL
A-B
M
0.20 DC
5 8
PLATING
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
P1-P3P4-P6P7-P9P10-P11

MPC9447AC

Mfr. #:
Buy MPC9447AC
Manufacturer:
NXP / Freescale
Description:
Clock Buffer 2.5 3.3V 250MHz Clock Generator
Lifecycle:
New from this manufacturer.
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