ADC1005S060_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 18
Integrated Device Technology
ADC1005S060
Single 10 bits ADC, up to 60 MHz
[1] The rise and fall times of the clock signal must not be less than 0.5 ns.
[2] The input admittance is
[3] Analog input voltages producing code 0 up to and including code 1023:
a) V
offset
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(V
RB
) at T
amb
= 25 C.
b) V
offset
TOP is the difference between the reference voltage on pin RT (V
RT
) and the analog input which produces data outputs equal
to code 1023 at T
amb
= 25 C.
[4] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors R
OB
and R
OT
as shown in Figure 3.
a) The current flowing into the resistor ladder is
I
V
RT
V
RB
–
R
OB
R
L
R
OT
++
---------------------------------------
=
and the full-scale input range at the converter, to cover code 0
to 1023 is
V
I
R
L
I
L
R
L
R
OB
R
L
R
OT
++
---------------------------------------
V
RT
V
RB
+ 0.8375 V
RT
V
RB
–== =
b) Since R
L
, R
OB
and R
OT
have similar behavior with respect to process and temperature variation, the ratio
R
L
R
OB
R
L
R
OT
++
---------------------------------------
will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends
mainly on the difference V
RT
V
RB
and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[5]
E
G
V
1023
V
0
–V
ip p–
–
V
ip p–
-------------------------------------------------------
100=
[6] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
[7] The analog input settling time is the minimum time required
for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
[8] Effective bits are obtained via a Fast Fourier Transform (FF
T) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to
signal-to-noise ratio: S/N = ENOB 6.02 + 1.76 dB.
[9] Intermodulation measured relative to either tone with analog in
put frequencies of 4.3 MHz and 4.5 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter.
[10] Output data acquisition: the output data is available af
ter the maximum delay time of t
d(o)
. IDT recommends the lowest possible output
load. These parameters are guaranteed by characterization and not by production test.
C
L
load capacitance - - 10 pF
SR slew rate V
CCO
= 2.7 V 0.2 0.3 - V/ns
3-state output delay times (f
clk
= 60 MHz; V
CCO
= 3.3 V); see Figure 5
t
dZH
float to active
HIGH delay time
- 16 20 ns
t
dZL
float to active
LOW delay time
- 30 34 ns
t
dHZ
active HIGH to
float delay time
- 25 30 ns
t
dLZ
active LOW to
float delay time
- 23 27 ns
Table 6. Characteristics …continued
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
C to 70
C; typical values
measured at V
CCA
= V
CCD
= 5 V; V
CCO
= 3.3 V; V
RB
= 1.3 V; V
RT
= 3.7 V; C
L
= 10 pF and T
amb
= 25
C unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
