© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 2
1 Publication Order Number:
NTMD2P01R2/D
NTMD2P01R2
Power MOSFET
−2.3 Amps, −16 Volts
Dual SOIC−8 Package
Features
• High Efficiency Components in a Single SOIC−8 Package
• High Density Power MOSFET with Low R
DS(on)
• Logic Level Gate Drive
• SOIC−8 Surface Mount Package,
Mounting Information for SOIC−8 Package Provided
• Pb−Free Packages are Available
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage V
DSS
−16 V
Gate−to−Source Voltage − Continuous V
GS
"10 V
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 100°C
Pulsed Drain Current (Note 4)
R
q
JA
P
D
I
D
I
D
I
DM
175
0.71
−2.3
−1.45
−9.0
°C/W
W
A
A
A
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 100°C
Pulsed Drain Current (Note 4)
R
q
JA
P
D
I
D
I
D
I
DM
105
1.19
−2.97
−1.88
−12
°C/W
W
A
A
A
Thermal Resistance − Junction−to−Ambient
(Note 3)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 100°C
Pulsed Drain Current (Note 4)
R
q
JA
P
D
I
D
I
D
I
DM
62.5
2.0
−3.85
−2.43
−15
°C/W
W
A
A
A
Operating and Storage
Temperature Range
T
J
, T
stg
−55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= −16 Vdc, V
GS
= −4.5 Vdc, Peak I
L
= −5.0 Apk, L = 28 mH, R
G
= 25 W)
E
AS
350 mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
L
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), Steady State.
3. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
P−Channel
D
S
G
http://onsemi.com
V
DSS
R
DS(ON)
Typ I
D
Max
−16 V
100 mW @ −4.5 V
−2.3 A
SOIC−8
SUFFIX NB
CASE 751
STYLE 11
MARKING DIAGRAM*
AND PIN ASSIGNMENT
ED2P01= Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
ED2P01
AYWW G
G
1
8
1
8
S1 G1 S2 G2
D1 D1 D2 D2
*For additional marking information, refer to
Application Note AND8002/D.
(Note: Microdot may be in either location)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
Device Package Shipping
†
ORDERING INFORMATION
NTMD2P01R2 SOIC−8 2500/Tape & Reel
NTMD2P01R2G SOIC−8
(Pb−Free)
2500/Tape & Reel
